Signal Integrity Fundamentals
Transmission Lines, Impedance Matching, Crosstalk & Termination Strategies
1. Introduction — When a PCB Trace Becomes a Transmission Line
At low frequencies, a PCB trace is just a wire: a few milliohms of resistance, negligible in the design. But when the signal’s rise time becomes comparable to the propagation delay across the trace — roughly when the trace length exceeds one-sixth of the signal’s rising-edge length — the trace stops behaving as a lumped element and starts behaving as a transmission line. Reflections, ringing, crosstalk, and radiated emissions follow. This guide develops the transmission-line model, the concept of characteristic impedance Z0, the reflection mechanism, termination strategies, crosstalk, eye diagrams, and the stackup decisions that keep a 1 Gbps+ bus error-free.
The threshold is easy to estimate: edge length Ledge = tr × v (propagation speed ≈ 6 in/ns on FR-4 surface microstrip, ≈ 5.3–5.7 in/ns on inner layers). If the trace is longer than Ledge/6 ≈ tr × 1 in/ns, you must treat it as a transmission line. For a 1 ns rise time, that’s roughly 1 inch — most modern high-speed buses exceed this quickly.
2. Transmission Line Theory and Propagation
2.1 Distributed L and C Model
A trace over a ground plane has distributed inductance L′ (nH/in) and capacitance C′ (pF/in). The line is modeled as an infinite ladder of these per-unit-length elements. Two parameters fall out of this model:
Propagation delay per unit length: tpd = √(L′·C′)
For FR-4 (εr ≈ 4.2): tpd ≈ 85 ps/in on surface microstrip, ≈ 180 ps/in = 5.5 in/ns on inner stripline.
Important property: for a lossless line, Z0 is real and independent of frequency and length — it is the ratio of voltage to current for a traveling wave, NOT a resistance you can measure with a DC ohmmeter.
2.2 Computing Z0 — Common Geometries
For a microstrip (trace on the outer layer over a solid plane):
Z0 ≈ (87/√(εr+1.41)) · ln(5.98·h / (0.8·w + t)) [for w/h < 1]
Edge-coupled differential pair: Zdiff ≈ 2·Z0·(1 − 0.48·e(−0.96·s/h)), s = edge-to-edge spacing
Worked Example — 50 Ω microstrip on FR-4:
h = 8 mil (0.2 mm), εr = 4.2, t = 1.4 mil:
Solve 50 = (87/√5.61)·ln(5.98·8/(0.8w+1.4)) → w ≈ 14–15 mil → w ≈ 14.5 mil for 50 Ω.
With 4 mil spacing on a 4-mil gap, differential Zdiff ≈ 2·50·(1−0.48·e(−0.96·4/8)) = 100·(1−0.48·0.619) ≈ 100·0.703 ≈ 70 Ω (too low for 100 Ω — widen gap to ~8 mil).
| Geometry | Typical Z0 (FR-4) | Use Case |
|---|---|---|
| Surface microstrip, w=8 mil, h=5 mil | ≈50 Ω | Single-ended, outer layer |
| Symmetric stripline, w=6 mil, h=8+8 mil | ≈50 Ω | Inner layer, best shielding |
| Differential pair, 5 mil w / 8 mil gap, h=5 mil | Zdiff ≈ 100 Ω | USB / LVDS / PCIe |
| Coaxial cable RG58 | 50 Ω | Reference for connector design |
3. Reflections and Impedance Mismatch
3.1 The Reflection Coefficient
When a wave traveling down a line of impedance Z0 encounters a load ZL, part is absorbed and part reflected. The reflection coefficient at the load is:
ΓL = (ZL − Z0) / (ZL + Z0)
ZL = Z0 → Γ = 0 (no reflection, matched)
ZL = ∞ (open) → Γ = +1 (full positive reflection, voltage doubles)
ZL = 0 (short) → Γ = −1 (full negative reflection, voltage inverts)
Return loss (dB): RL = −20·log10|Γ|. A 10% mismatch (ZL = 45 Ω vs 50 Ω) → Γ = 0.053 → RL ≈ 25.6 dB.
3.2 Ringing and the Two-Trip Delay
An unterminated 3-inch trace driven by a fast source shows a characteristic staircase: the signal reflects at the open far end, returns, reflects again at the low-impedance source, and settles after multiple round trips. The period of the ringing is related to 2× the propagation delay, and the overshoot magnitude depends on the source impedance vs Z0.
A 10 Ω driver into 50 Ω: ΓS = −0.67 → strong secondary reflections → ringing.
Critical length rule: if 2·tpd·L > tr (round-trip longer than rise time), reflections fully develop and termination becomes mandatory.
Example: tr = 1 ns, tpd = 85 ps/in → critical length ≈ 1 ns/(2·85 ps/in) ≈ 5.9 inches. Under that, ringing partially hides in the edge — but noise margin is still consumed.
3.3 Worked Example — Computing Step Response Overshoot
Step 1 — initial wave: Vinit = VDD·Z0/(ZS+Z0) = 3.3·50/60 = 2.75 V.
Step 2 — at open load: ΓL = +1 → far-end voltage = 2·2.75 = 5.5 V (overshoot to 167%).
Step 3 — reflected wave returns to source: ΓS = (10−50)/60 = −0.667 → next level = 5.5 − 0.667·(2.75) ≈ 5.5−1.83 = 3.67 V.
Step 4 — settles toward 3.3 V with alternating steps ≈ every 2·tpd·L.
Result: ≥ 60% overshoot and multi-ns settling — dangerous for receivers with limited input range. Fix: series termination (§4.1).
4. Termination Strategies
4.1 Series (Source) Termination
Place a resistor RS in series at the source such that RS + ZS = Z0. The initial wave is then exactly VDD/2 at the line input; it travels to the open far end, reflects back with +1, and arrives at the load at full VDD. Because the far end is open (ΓL=+1), the load sees a clean full-amplitude edge with no further reflection when the return wave is absorbed by the matched source.
RS = Z0 − ZS (driver output impedance, often 5–20 Ω)
Example: 50 Ω line, driver ZS = 12 Ω → RS = 38 Ω → 39 Ω (E24).
Pros: lowest power, one resistor, no DC load. Cons: far-end voltage only full after 2·tpd — unusable for bidirectional busses or very long lines where the half-amplitude intermediate state violates receiver thresholds.
4.2 Parallel (End / DC) Termination
A resistor RL = Z0 at the far end absorbs the wave immediately. Simplest form: single resistor to ground or to the termination rail (VTT = VDD/2). This guarantees a single clean edge but draws DC current (VDD²/Z0 ≈ 200 mW at 3.3 V / 50 Ω).
4.3 Thévenin (Split) Termination
Two resistors R1∥R2 = Z0 and their divider set to VDD/2: e.g., 100 Ω to VDD and 100 Ω to ground gives 50 Ω equivalent with a 1.65 V bias for 3.3 V logic. Common in TTL-era and clock distribution; more resistors but handles bidirectional signals and sets a solid idle level.
4.4 AC Termination
An R∥C network (R = Z0, C chosen so its impedance is small at the signal frequency but open at DC) at the load. Terminates the AC signal while consuming no DC power — ideal for battery and high-fanout applications, but C must be sized correctly and it slows the DC settling.
| Strategy | Placement | Power Draw | Bidirectional? | Best For |
|---|---|---|---|---|
| Series RS | Near source | ~0 (CMOS) | Point-to-point only | Point-to-point clocks, memory, GPIO |
| Parallel (to VTT) | Far end | DC, V²/R | Yes | Long single-ended, termination rail available |
| Thévenin split | Far end | DC, V²/R | Yes | Legacy logic, no VTT rail |
| AC R∥C | Far end | ~0 DC | Yes (careful) | Low-power, high fan-out clock trees |
| Differential (100 Ω) | Far end, across pair | Low | Yes | LVDS, USB, Ethernet |
5. Crosstalk and Spacing Rules
5.1 Capacitive and Inductive Coupling
Crosstalk arises from two coupling mechanisms between adjacent traces: mutual capacitance Cm (electric field) coupling current into the victim, and mutual inductance Lm (magnetic field) coupling a voltage. The near-end crosstalk (NEXT) appears immediately at the aggressor’s drive end; the far-end crosstalk (FEXT) appears at the far end after one propagation delay.
Kb ≈ 1/(4·(1 + s/h)²) — where s = spacing, h = dielectric height
Rule of thumb: 3W spacing (s = 3× trace width) keeps Kb below ≈ 2–5% for typical FR-4 microstrip; 2W is the absolute minimum for non-critical nets.
Far-end crosstalk (microstrip, inhomogeneous):
Kf ≈ (tpd/4)·(Cm/C′ − Lm/L′)·L — grows linearly with length L; stripline (homogeneous) minimizes FEXT.
5.2 Spacing vs Data Rate — Practical Table
| Signal Class | Typical Edge Rate | Min Spacing | Notes |
|---|---|---|---|
| Slow control / I2C | ≥ 100 ns | 1W–2W | Crosstalk negligible |
| SPI / DDR data | 1–2 ns | 3W | Keep away from clocks |
| Clocks / strobes | 0.5–1 ns | 3W–5W + guard trace/ground | Aggressors; isolate |
| DDR4/5 DQ-DQS | 100–300 ps | Per JEDEC, ≥ 2× mil / length matched | Simulate; spacing & length tuning |
| Differential pairs | 50–150 ps | Pair-to-pair ≥ 3× pair width | Keep pairs coupled |
6. Eye Diagram Analysis
An eye diagram is the superposition of many unit intervals (UI) of a high-speed signal, triggered on the clock. It is the single most useful measurement for judging digital signal integrity. Key parameters read directly from the eye:
Eye height = VIH−VIL margin after noise and ISI (want > 200 mV at receiver)
Eye width = usable time window (want ≥ 0.5–0.6 UI after jitter)
Jitter p-p and RMS (TJ = 14·DJ + RJ·factor at BER 1e-12)
Rise/fall time, overshoot, undershoot
Mask test: the eye must stay outside the mask polygon (per USB/PCIe/GbE specs). Violations → reduce ISI, crosstalk, or jitter.
A closed or “smearing” eye usually indicates one of: excessive reflections (poor termination), crosstalk from a nearby aggressor, excessive ISI from long lossy lines (skin effect + dielectric loss), or supply/clock jitter. Decompose with a BER contour or bathtub curve to separate deterministic (DDJ, crosstalk) from random (RJ) jitter.
7. Vias, Layer Changes and Their Impact
7.1 Via as a Discontinuity
Every via introduces a capacitance (≈0.2–0.5 pF from the barrel to surrounding planes, plus the non-functional pad and the stub), an inductance (≈0.1–1 nH depending on length and return path), and a stub of unterminated barrel below the target layer. At 1–5 Gbps these show up as: impedance dip, added insertion loss, and reflected energy — measurable as S21 ripple and S11 notches.
Cvia ≈ 1.41·εr·Dpad·T / (Dhole−Dpad) [fF]
Lvia ≈ 5.08·h·(ln(4·h/d) + 1) [nH], h = via length (mm), d = diameter
Minimize by: back-drilling (removes stub), smaller drill + pad, no non-functional pads, symmetric ground vias around the signal via, routing on one layer when possible.
7.2 Return Path and Plane Cuts
Whenever a trace changes layers, its return current must also change reference plane. If there’s no nearby via or the planes are split, the return current detours through a slot/cut — creating a large loop inductance that spikes noise and causes crosstalk. Rules: place a ground via within ~50–100 mil of each signal via, never route over plane splits, and use reference planes (GND preferred over power) for all high-speed layers.
8. Stackup Design for SI
| Stackup | Layers | SI Quality | Typical Use |
|---|---|---|---|
| 1S2P | 2 signal + 2 plane | Poor for high speed | Simple MCU boards < 50 MHz |
| 4-layer | S/G/P/S | OK up to ~1 Gbps (surface) | General embedded, USB2, 100M Eth |
| 6-layer (SIG/GND/SIG/PWR/SIG/GND) | 4 sig + 2 planes | Good; inner stripline well shielded | DDR3/4, GbE, high-speed ADC |
| 8+ layer | Multiple planes + buried vias | Excellent, controlled impedance | PCIe, 10+ Gbps SERDES |
Best-practice stackup rules: (1) every signal layer adjacent to a solid ground plane; (2) symmetric stackups avoid warpage and keep impedance consistent; (3) use stripline for the most critical nets to eliminate FEXT; (4) specify controlled impedance (±10% at least, ±5% preferred) on the fabrication drawing, with impedance coupons on the panel edge for verification.
9. Worked Example — 100 Ω Differential Pair Design for LVDS
Step 1 — pick single-ended Z0: for a well-spaced pair, Z0 ≈ 50 Ω (odd-mode 50).
Step 2 — find width: 50 Ω microstrip, h=5, εr=4.2, t=1.4 → w ≈ 9 mil.
Step 3 — set spacing: Zdiff = 2·Z0·(1−0.48·e−0.96·s/h) = 100 → 0.48·e−0.96s/5 = 0 → for exactly 100 with strong coupling, s small. Solve: e−0.96·s/5 = (1−100/(2·50))/0.48 = 0/0.48 → use finite: with Z0=50 the un-coupled Zdiff=100 already; target actual ≈ s=8 mil → check: 0.48·e−0.96·8/5=0.48·e−1.536=0.48·0.215=0.103 → Zdiff=2·50·(1−0.103)=89.7 Ω → slightly low; increase spacing to 10 mil → Zdiff≈94 Ω; or raise Z0 to 52 by widening… final: w=8 mil, s=10 mil, verify by field solver.
Step 4 — length match: keep intra-pair skew < 5 mil (≈ 0.8 ps), pair-to-pair skew per spec; add serpentine only if length difference > ~50 mil.
Step 5 — verify with simulator: extract S-parameters, check Sdd21 flatness < 1 dB over band and no resonance from vias/connectors.
10. Common SI Mistakes
- Treating every trace as a wire: ignoring the transmission-line threshold; critical length exceeded with no termination.
- No reference plane under the trace: routing over a split or on the edge of the board with no return path → huge loop inductance.
- Vias without ground vias / with long stubs: unexplained insertion-loss ripples and reflection notches at GHz.
- Inconsistent spacing on differential pairs: widening in one section changes Zdiff, causing mode conversion.
- Ignoring connector and package discontinuities: the PCB is matched but the BGA pad/connector isn’t.
- Measuring with wrong probing: probe ground lead inductance corrupts the eye; use differential probe with short ground.
- Choosing termination based only on signal, not topology: using series termination on a bidirectional bus, or AC termination with too-small C that blocks the DC level.
11. Frequently Asked Questions
Q1. When exactly do I need to worry about impedance matching?
When trace length > tr/6 (about 1 inch per 1 ns of rise time on FR-4) or the bus exceeds ~100 MHz / 200 Mbps for single-ended. Then match Z0 and terminate.
Q2. What is the difference between impedance matching and termination?
Matching sets the line’s Z0 (by geometry) to a target; termination adds a network at the source/load so reflections don’t occur. You need both: matched line + terminator.
Q3. Is 50 Ω universal?
50 Ω is a convenient compromise between loss and power-handling for single-ended; 75 Ω minimizes cable attenuation (video); differential buses standardize at 100 Ω (LVDS, USB, PCIe, Ethernet). Always follow the interface’s standard.
Q4. Does a ground pour between traces always help?
Yes for crosstalk (reduces coupling), but it increases capacitance and lowers Z0, and can create resonances if not stitched. Use guard traces with vias only for the most critical nets.
Q5. Why is my eye still closed even with proper termination?
Check (a) connector/package discontinuities, (b) via stubs, (c) reference-plane continuity, (d) power-plane noise, (e) jitter from the clock, (f) crosstalk from a second aggressor — termination fixes only reflections.
Q6. How do I verify a stackup’s impedance without expensive tools?
Use the fab’s impedance coupon (test strips on the panel) and a TDR or VNA; free field-solver calculators (e.g., Saturn PCB Toolkit, KiCad’s impedance calculator) give good first estimates; then confirm on the coupon.