Op-Amp Stability and Compensation Guide
Gain Margin, Phase Margin & Bode Plot Analysis
1. Introduction — Why Op-Amps Oscillate
Every operational amplifier contains internal gain stages that dominate its open-loop frequency response. A feedback network wrapped around that gain can convert a perfectly linear amplifier into an oscillator if the loop’s phase shift reaches 180° before the loop gain drops below unity. This guide builds a rigorous framework — based on the loop gain T(s), the Bode plot, and the two stability metrics (gain margin and phase margin) — that lets you predict, measure, and fix instability before it appears on your lab bench as a squealing or ringing output.
Op-amp instability is one of the most common causes of field failures in analog designs: op-amps configured as unity-gain buffers driving a few hundred picofarads of cable or a long PCB trace can oscillate at 5–50 MHz; high-speed amplifiers into capacitive loads show step-response ringing and 10–20 dB of peaking. The cure is almost never “add a bigger capacitor” blindly — it is a deliberate compensation network chosen from the loop-gain perspective developed here.
2. Open-Loop Gain, Bandwidth and the Gain-Bandwidth Product
2.1 The Single-Pole Dominant Rolloff
A well-compensated voltage-feedback op-amp is designed to behave like a single-pole system over most of its bandwidth. Its open-loop gain can be modeled as:
A(s) = A0 / (1 + s / ωp1)
Where A0 is the DC open-loop gain (typically 100–120 dB) and fp1 = ωp1/2π is the dominant pole, typically 5–100 Hz.
Gain-bandwidth product: ft = A0 × fp1
On the −20 dB/decade portion: A(f) × f = ft (constant), so a gain-of-10 amplifier closes at fcl = ft/10.
Real amplifiers deviate from the ideal single-pole model at high frequency with a second and third pole (typically 0.5×–3× the unity-gain frequency ft), plus a zero from the input stage. Those parasitic poles are exactly what rob the loop of phase margin at high gains.
2.2 Typical Device Parameters
| Parameter | TL072 (JFET) | OPA2134 | LM7171 (CFB-like) | OPA656 (wideband) |
|---|---|---|---|---|
| Unity-gain BW ft | 3 MHz | 8 MHz | 100 MHz | 220 MHz |
| A0 (DC gain) | 106 dB | 110 dB | 65 dB | 70 dB |
| Dominant pole | ≈15 Hz | ≈25 Hz | ≈500 Hz | ≈500 Hz |
| Second pole fp2 | ≈6 MHz | ≈15 MHz | ≈300 MHz | ≈400 MHz |
| PM at unity gain | ≈55–60° | ≈60° | ≈45° | ≈50° |
3. Loop Gain, Gain Margin and Phase Margin — Definitions
3.1 The Loop Gain T(s)
Consider a negative-feedback amplifier with forward gain A(s) and feedback factor β (the fraction of output returned to the inverting input). The closed-loop gain is:
Acl(s) = A(s) / (1 + A(s)·β) = A(s) / (1 + T(s))
Loop gain: T(s) = A(s)·β
Stability condition (Nyquist / Bode criterion): the system is stable if the closed-loop poles stay in the left half-plane — equivalently, if at the frequency where |T(jω)| = 1 (0 dB), the phase of T is above −180° by the phase margin, and at −180° the magnitude is below 0 dB by the gain margin.
For a non-inverting amplifier with feedback resistors Rf and Rg: β = Rg/(Rg+Rf) = 1/(1 + Rf/Rg), i.e. β = 1/Acl(noise). Higher closed-loop gain means lower β, which pushes the loop-gain crossover to lower frequency where more phase remains — this is why a gain-of-10 stage is inherently more stable than a unity-gain follower.
3.2 Phase Margin and Gain Margin — Judgment Criteria
| Metric | Definition | Typical Target | Observed Symptom if Low |
|---|---|---|---|
| Phase Margin (PM) | 180° + ∠T(jω) evaluated at |T| = 0 dB | ≥ 45° (robust: 60°) | Step ringing, peaking in AC response |
| Gain Margin (GM) | −|T| (dB) at the frequency where ∠T = −180° | ≥ 6–10 dB | Low-Q oscillation tendency, phase-margin runaway |
| PM → overshoot | For 2nd-order approx: %OS ≈ 100·exp(−π·ζ/√(1−ζ²)), ζ ≈ PM/100 | PM 45°→ ≈23% OS | Visible overshoot on step |
| PM = 0° | Oscillation condition | Never | Sustained oscillation at fosc |
PM ≈ 30° → overshoot ≈ 50%, heavy ringing
PM ≈ 45° → overshoot ≈ 23%, acceptable for most
PM ≈ 60° → overshoot ≈ 8–9%, near-flat (optimum damping, ζ≈0.6)
PM ≈ 75° → no overshoot, sluggish settling
4. Bode Plot Analysis — Reading the Loop
4.1 Constructing the Bode Plot of T(jω)
Because the loop gain is the product A(s)·β, its Bode magnitude is the open-loop gain magnitude shifted down by 1/β (i.e., by −20·log10(β) dB), and its phase is exactly the open-loop phase. On a log–log plot you can therefore draw the loop-gain curve simply by drawing a horizontal line at the noise gain (1/β in dB) and subtracting it from the A(s) curve.
Procedure to evaluate stability from the Bode plot:
- Plot |A(jω)| (dB) and ∠A(jω) (deg) on a log-frequency axis — from the datasheet or a simulation.
- Draw the noise-gain line: 20·log10(1/β) dB horizontal.
- The intersection of the noise-gain line with |A| is the crossover frequency fc where |T| = 1 (0 dB).
- Read the loop phase at fc: PM = 180° + ∠T(fc).
- Find where ∠T = −180° and read |T| there: GM = −|T(f−180)| in dB.
Each pole contributes −90° asymptotically (≈ −45° at fp), each zero +90° (+45° at fz).
A 2-pole loop has −180° total phase → zero PM unless gain crosses 0 dB before the second pole.
This is why a dominant-pole compensated amp must have its crossover well below fp2.
5. Stability of Inverting vs Non-Inverting Amplifiers
5.1 Noise Gain Is What Matters
The stability of a feedback amplifier is governed by the noise gain 1/β, not by the signal gain. Both topologies have the same loop gain T = A·β; what differs is where the signal enters.
| Aspect | Non-Inverting | Inverting |
|---|---|---|
| Signal gain | 1 + Rf/Rg | −Rf/Rg |
| Noise gain 1/β | 1 + Rf/Rg (same as signal gain) | 1 + Rf/Rg (higher than signal gain) |
| Bandwidth | ft/(1+Rf/Rg) | Same — set by noise gain |
| Stability for same signal gain | Identical — both see same noise gain | Identical loop gain |
| Unity-gain buffer | 1/β = 1 (worst case, least stable) | Rg→∞: 1/β→1 also (same) |
Practical consequence: a unity-gain buffer (1/β = 1) is the most stressful configuration — crossover sits at ft where the second pole already steals ~30–60° of phase. An inverting gain-of-1 (Rf = Rg) has signal gain of 1 but noise gain of 2, so it is actually more stable than the buffer. Always reason about the noise gain line on the Bode plot, never the signal gain alone.
5.2 Simulation Snippet — Measuring Loop Gain in LTspice
V(loop) = −(V(x)·V(y)/V(i)) using the Tian probe:
Insert a large inductor L=1G in series with the feedback break and a 1V AC source; run .AC analysis. LTspice .NET / .PROBE can directly output the loop gain magnitude and phase.
.ac dec 100 1 10meg
.probe V(loopgain)
.param ft=10meg
Measure at 0 dB: read ∠T → PM = 180 + ∠T.
Measure at −180°: read |T| → GM in dB.
6. Capacitive Load Instability — Root Causes
6.1 How CL Destroys Phase Margin
A capacitive load CL on the output forms a pole with the op-amp’s open-loop output impedance Ro (typically 50–200 Ω):
With Ro = 100 Ω and CL = 1 nF → fp ≈ 1.6 MHz — right at the crossover of a 10 MHz amplifier!
This pole adds another −90° before crossover, collapsing PM from 60° toward 0° or negative → ringing then oscillation. The feedback network, however, samples the output node after Ro, so the feedback loop includes this pole and the open-loop output impedance — exactly the mechanism that destabilizes unity-gain buffers driving long cables.
Three symptoms to recognize: (1) step response overshoot > 30% with multiple ringing cycles; (2) peaking of 10–20 dB in the AC response near ft/10; (3) sustained oscillation when CL exceeds a critical value — many datasheets specify a “capacitive load drive” curve for exactly this reason.
6.2 Quantitative Example
Ro ≈ 65 Ω → fp = 1/(2π·65·500p) = 4.9 MHz
ft = 8 MHz, so crossover is near/after the load pole.
Second pole ≈ 15 MHz adds −45° at 8 MHz; load pole adds ≈ −60° at 4.9 MHz.
Resulting PM ≈ 60 − 45 − 60 = −45° → unstable, oscillates ≈ 4–8 MHz.
Cure options quantified in §7.
7. Compensation Networks — Leading, Lagging, Riso and CF
7.1 Feedback Capacitor CF (Lead / Zero Compensation)
Placing a small capacitor CF across Rf creates a feedback zero that cancels the pole formed by CL and the feedback network’s source impedance. The zero frequency and the pole it introduces at higher frequency are:
fz = 1 / (2π·Rf·CF) — place this to cancel the load pole
Choose: CF = CL·Ro/Rf (for Ro the open-loop output resistance)
Rule of thumb: for a non-inverting buffer driving CL:
CF ≈ √(CL/(2π·Rf·ft)) for a well-damped response (see TI precision labs).
Because CF also acts as a low-pass on the noise gain (it raises 1/β at high frequency via the parallel path), it reduces high-frequency noise and can also be used to roll off bandwidth intentionally — but be aware it creates a pole at fp2′ ≈ 1/(2π·Rf·CF·(1+Rg/Rf)) that must sit above crossover.
7.2 Series Isolation Resistor Riso
The classic cure for capacitive-load instability: insert Riso between the op-amp output and CL. Now the feedback can be taken either before Riso (output-of-amp) or after it (output-of-network):
- Feedback before Riso: Riso + CL become an output filter, outside the loop. The loop sees CL only through Riso in series with Ro, pushing the pole to fp = 1/(2π·(Ro+Riso)·CL) — lower pole but the load-pole phase is decoupled from the loop.
- Feedback after Riso: introduces a zero in the loop at fz = 1/(2π·Riso·CL), boosting phase near crossover — restores margin but adds a pole later.
Riso ≈ √(Ro/(2π·CL·ft)) — gives ~10–20% overshoot (Q ≈ 0.7–0.9)
Example: Ro=65 Ω, CL=500 pF, ft=8 MHz → Riso ≈ √(65/(2π·500p·8M)) ≈ √(65/0.0251) ≈ 51 Ω → use 47 Ω.
Trade-off: adds a DC-series error (negligible for buffering into an ADC input) and forms a divider if the load has finite resistance.
7.3 Lag Compensation and Feedforward
| Method | Network | Effect on Loop | When to Use |
|---|---|---|---|
| Feedback CF (lead) | Cap across Rf | Adds zero, raises 1/β at HF → recovers PM | Capacitive load, HF noise reduction |
| Riso isolation | Series R before CL | Decouples load pole from loop | Buffers, ADC drivers, cable driving |
| Lag (dominant-pole) comp | External C at compensation pin | Lowers fp1, moves crossover down | Specialty amps w/ comp pin (e.g. OPA37) |
| Noise-gain shaping | Rg||Cg to ground | Raises 1/β only at HF (Cg shorts Rg) | Improve stability at higher signal gain |
| Out-of-loop output filter | Riso+C after feedback node | No loop effect, pure load filter | When stability already OK, just filter |
8. Loop-Gain Simulation and Measurement Techniques
8.1 Simulation Approaches
- Tian method (Middlebrook-Tian): the most accurate loop-gain extraction. Breaks the loop with a pair of dependent sources; plots T(s) directly. Built into LTspice (.NET command) and most Spice variants.
- Voltage-injection (Middlebrook): inject a small AC source in series in the feedback path and compute T = Vret/Vinj − 1. Slightly less accurate when loop gain is very high.
- Transient step test: apply a small step (or square wave) to the input, observe V(out) overshoot and ringing; relate overshoot to PM via the PM–overshoot chart. Fastest sanity check, works on real hardware too.
1. Break the feedback path at the summing node; insert a 1:1 isolation transformer.
2. Drive the injection port with the network analyzer’s output (10 mV, swept).
3. Measure the ratio and phase across the break: this is T(jω).
4. Read PM at 0 dB; GM at −180°.
Targets: PM ≥ 45° (60° preferred), GM ≥ 10 dB for production robustness across temperature and unit-to-unit variation.
9. Common Instability Symptoms and Troubleshooting
| Symptom | Likely Root Cause | Diagnosis | Fix |
|---|---|---|---|
| Step ringing / overshoot > 30% | PM 20–40° (capacitive load, high Rf) | Step test; AC peaking check | Add Riso or CF; reduce Rf |
| Sustained oscillation 5–50 MHz | PM ≤ 0°, capacitive load beyond spec | Oscilloscope FFT; touch CL to confirm | Riso in series; feedback after Riso |
| High-frequency burst at power-on | Supply decoupling absent; loop parasitic | Check 0.1 µF + 10 µF per supply pin | Add local decoupling, star ground |
| Output spikes when load switches | Inductive load / long trace L in loop | Probe load side, look for L-C ringing | Riso, snubber, feedback at load |
| DC offset + HF noise increase | Excessive Rf, parasitic Cin on −input | Bode: crossover too high | CF across Rf, lower Rf |
| Oscillation only with probe connected | Probe Cp (≈10 pF) adds load pole | Use ×10 probe, 100 MHz+ | None needed — artifact; verify with active probe |
10. Worked Example — Compensating a Buffer Driving 1 nF Cable
Step 1 — check stability: Ro=65 Ω, CL=1 nF → fp=1/(2π·65·1n)=2.45 MHz; ft=8 MHz → clearly unstable (PM<0).
Step 2 — choose Riso:
Riso ≈ √(Ro/(2π·CL·ft)) = √(65/(2π·1n·8M)) = √(65/0.0503) ≈ 36 Ω → 33 Ω (E24)
New output pole with feedback after Riso: fp’ = 1/(2π·(65+33)·1n) = 1.6 MHz (zero at 4.8 MHz restores phase).
Step 3 — verify bandwidth: RC filter (Riso+Ro)·CL → −3 dB at 1.6 MHz > 100 kHz signal ✓. For higher BW use feedback-after-Riso with a small CF.
Step 4 — simulate: Tian loop-gain plot should show PM ≥ 50°, GM ≥ 12 dB. Step test: overshoot < 20%, settle < 2 µs.
11. Common Mistakes
- Confusing signal gain with noise gain when predicting stability — always compute 1/β.
- Ignoring the load pole from CL formed with Ro; adding an output cap “for filtering” without Riso invites oscillation.
- Blindly adding CF large enough to also kill bandwidth, or placing its zero below crossover (destroys GM).
- Using a 1× scope probe (≈100 pF) to “verify” stability — the probe itself changes CL and can show false ringing.
- Not checking stability across temperature and supply — PM shrinks as A0 and Ro vary.
- Neglecting feedback-node parasitic capacitance to ground at the inverting input; it forms a pole with Rf that degrades PM (cured with CF).
- Drawing conclusions from a single simulation corner — run min/max supply, load, and temperature corners.
12. Frequently Asked Questions
Q1. Why does my unity-gain buffer oscillate but the same op-amp at gain 10 is fine?
At unity gain, 1/β = 1 pushes crossover to ft where the second pole already reduces phase. At gain 10, crossover is at ft/10, well before the second pole, preserving PM.
Q2. What phase margin should I target?
45° minimum for guaranteed stability; 60° for low overshoot (≈8%) and robust production margin; 75°+ if settling time matters more than bandwidth.
Q3. Can I always fix a capacitive load with Riso?
For most voltage-feedback amps, yes — sized via the Riso formula. For current-feedback amps the mechanism differs (they are more sensitive to feedback capacitance), so check the datasheet’s recommended compensation.
Q4. How do I measure loop gain on real hardware?
Network analyzer with a series injection transformer in the feedback path, measuring gain and phase across the break (Middlebrook). Or use a fast step input and infer PM from overshoot.
Q5. What does the CF do to my noise?
It low-pass-filters the noise gain (reduces high-frequency output noise) while restoring phase margin — a two-for-one benefit, provided the zero is placed at the right frequency.
Q6. My simulation says stable but the hardware rings — why?
Parasitic capacitance from PCB layout (inverting-input node, output trace), unmodeled CL, package/ESD diodes, and missing supply decoupling all add poles/spikes not in the ideal schematic. Add layout parasitics to the sim or compensate with margin.