1. Introduction — From a Tiny Physical Change to a Clean Digital Number

A sensor signal chain has one job: convert a small, high-impedance, noisy physical signal into a low-impedance voltage that a data converter can digitize with the required accuracy. Between the sensor and the ADC sit the excitation source, the bridge or transducer network, the instrumentation amplifier, the anti-alias filter, and the reference — and each contributes offset, drift, noise and gain error. Designing the chain by picking parts from a datasheet headline (an amplifier’s “low noise” or an ADC’s “24-bit”) almost always fails, because errors that dominate at DC (offset, gain, drift, PCB leakage) are different from those that dominate at the signal band (noise, settling), and both are different from what limits resolution at the very low end (1/f noise, thermal EMF, charge injection). This guide builds the chain stage by stage, quantifies each error term, compares the bridge excitation options, derives the filter and ADC interface requirements, and ends with a complete worked example for a 2 mV/V load cell at 10 SPS. It complements the instrumentation amplifier and ADC front-end driver guides on this site.

2. Sensors, Bridges and Excitation

The dominant sensor topology in precision measurement is the Wheatstone bridge: four elements in a diamond, with the differential output V_out = V_exc · (ΔR/R) · 1/4 for a single active element (quarter bridge), or V_out = V_exc · (ΔR/R) for a full bridge. The key implications:

• The output is ratiometric with the excitation: a 2 mV/V load cell at 5 V excitation produces 10 mV at full scale. Using the same source as the ADC reference cancels the excitation drift, which is why ratiometric design is the default.
• Excitation current heats the bridge: the bridge’s self-heating raises the temperature and shifts the zero; the excitation must be low enough to keep the bridge power (and the temperature rise) acceptable — typically a few mW for a strain-gauge bridge.
• Excitation source options: a voltage source (simplest, but the bridge output varies with the supply), a current source (constant current removes the wiring resistance error and the bridge sensitivity depends on the bridge resistance), or a switched/AC excitation (rejects DC offsets and thermal EMF but requires demodulation).
• Wiring resistance matters: with a two-wire connection the lead resistance is in series with the bridge arm and creates a gain error; three- and four-wire (Kelvin) connections remove it.

The bridge is a differential, low-level source, so the first amplifier must have high common-mode rejection (CMRR) and high input impedance — the requirements that define the instrumentation amplifier.

3. The Instrumentation Amplifier Stage

A three-op-amp instrumentation amplifier (in-amp) presents high input impedance on both inputs, amplifies the differential signal with a single gain-setting resistor, and rejects the common-mode voltage. The gain is set by one resistor: G = 1 + 2R/R_gain for the classic three-op-amp topology, so the required R_gain = 2R/(G−1). The error terms that matter, in the order they usually limit a design:

Error term	Typical value	Referred to input	Mitigation
Input offset voltage	10–250 µV	Yes, full	Zero/calibrate; chopper or auto-zero if needed
Offset drift	0.1–2 µV/°C	Yes, full	Low-drift amp; thermal symmetry in layout
Gain error (R_gain tolerance)	0.1–1%	Proportional	0.1% resistor; system calibration
CMRR	80–120 dB	Vcm/CMRR	Matched source impedance; trims
Input bias current × source R	1–50 nA	I_b × R_source	Low-I_b amp; balance the source impedances
Noise (1/f + white)	10–50 nV/√Hz	Filtered by bandwidth	Band-limit early; choose voltage-noise vs current-noise for the source impedance

Two practical rules dominate the choice: (1) if the source impedance is high, current noise and bias current dominate — pick a low-I_b (CMOS or FET-input) amplifier; if the source is low impedance, voltage noise dominates — pick a bipolar low-V_n part. (2) A very high gain in one stage raises the noise gain and the CMRR error; a two-stage chain (moderate gain at the in-amp, extra gain at a second stage after filtering) is often better because the filter removes noise before the extra gain amplifies it. The differential-to-single-ended conversion, CMRR and gain details are the subject of the instrumentation amplifier design guide on this site; the gain-set resistor and the filter component arithmetic are handled directly by the ohms-law and filter calculators referenced below.

4. Filtering and Anti-Aliasing

The filter’s job is to band-limit the signal before the ADC sampling so that out-of-band noise and interference cannot alias into the band of interest. Requirements: (1) the passband must be flat and low-loss up to the signal band; (2) the stopband must attenuate everything above the Nyquist frequency (f_s/2); (3) the filter must not add noise or offset drift (the in-amp should precede it); (4) the settling must be compatible with the sampling rate — a high-order filter rings and slows the multiplexer settling in a multi-channel system. A practical anti-alias strategy for a low-frequency sensor (say 10–100 SPS) is a two-pole active low-pass with a corner just above the signal bandwidth and at least 40 dB of attenuation at the sampling rate; for higher sampling rates a higher-order filter or a delta-sigma converter’s own digital filter does the job. A Sallen-Key two-pole stage is the workhorse, and its component values are computed with the Sallen-Key filter calculator — set the corner for the anti-alias requirement and choose the Q for a maximally flat (Butterworth) response. For a simple single-pole RC pre-filter, the divider/filter arithmetic and the series/shunt resistor values follow the same ohms-law relations and can be checked with the Ohm’s law calculator.

5. The ADC Interface

The converter’s input structure defines the interface: a successive-approximation (SAR) ADC presents a switched capacitor that draws a current spike at each conversion, so the driving amplifier must settle to the required accuracy within the acquisition time; a delta-sigma ADC presents a more benign, continuous load but has its own input current and reference requirements. Key design points: (a) the amplifier’s output impedance and the ADC’s input capacitance form an RC that must settle to well below one LSB in the acquisition window; (b) the ADC reference sets the scale — a noisy reference is indistinguishable from a noisy signal, so the reference must be filtered and, for ratiometric bridges, shared with the excitation; (c) the differential input should be driven differentially where possible to double the signal and reject common-mode; (d) the ADC’s input range must be matched to the amplified signal with headroom for offset and overrange. A common failure is an amplifier that is fast enough on paper but whose settling is limited by the feedback network’s RC (a gain-set network with a large resistor and the amplifier’s input capacitance), producing a gain error that changes with the sampling rate.

6. The Error Budget

The error budget is where the design is proven or broken. Compute each term referred to the input (RTI), RSS the random terms, and add the systematic ones (offset, gain) separately because they can be calibrated:

Term	Value (RTI)	Type	Comment
In-amp offset	25 µV	Systematic, calibratable	Trim at zero load
Offset drift over 0–50 °C	5 µV	Systematic, drift	Low-drift part
Bridge + wiring mismatch	20 µV	Systematic	Kelvin connection
Amplifier noise (0.1–10 Hz)	2 µV p-p	Random	Band-limited by the filter
Reference noise	1 µV p-p	Random	Filtered reference
Quantization (16-bit, 5 V)	38 µV	Random	ADC LSB/√12

If the full-scale signal is 10 mV and the total RTI uncertainty is ~10 µV, the achievable resolution is 0.1% of full scale — which is what a 16-bit converter can deliver and what the budget must show before the parts are chosen. If the budget shows the noise dominating, band-limit; if the offset dominates, calibrate; if the reference dominates, improve the reference, not the amplifier.

7. Worked Example — 2 mV/V Load Cell, 10 SPS, 0.1% Accuracy

Target: a 350 Ω load cell, 2 mV/V, 5 V excitation (10 mV FS), 10 SPS, 0.1% of full scale resolution, 0–50 °C.

• Bridge output: 5 V × 2 mV/V = 10 mV FS. Bridge current 5 V/350 Ω ≈ 14.3 mA → bridge power ≈ 71 mW, acceptable for a metal-foil gauge with a reasonable thermal path (but keep the excitation duty low or the bridge temperature will drift the zero).
• Excitation: ratiometric — use one 5 V source for both the bridge and the ADC reference.
• Gain: map 10 mV to ~80% of the ADC’s input range; with a 5 V reference and a ±10 mV signal, a gain of about 200 gives 2 V, leaving headroom. For a three-op-amp in-amp with R = 25 kΩ, R_gain = 2 × 25 kΩ/(200−1) ≈ 251 Ω (a 0.1%, 25 ppm/°C resistor).
• Noise: a 20 nV/√Hz in-amp over a 10 Hz band gives ~20 nV/√Hz × √(1.57 × 10 Hz) ≈ 0.08 µV rms at the input — negligible; the 0.1–10 Hz 1/f noise of 2 µV p-p is the real limit and it is still small vs the 10 µV budget.
• Filter: at 10 SPS the Nyquist frequency is 5 Hz, so the anti-alias corner must sit below 5 Hz with enough order to attenuate the sampling-rate content by the required amount; place a 2 Hz Butterworth response with the Sallen-Key filter calculator and accept the correspondingly slower settling (roughly 5 time constants ≈ 0.4 s for a 2 Hz two-pole filter).
• ADC: a 16-bit delta-sigma at 10 SPS with a 5 V reference gives 76 µV/LSB — larger than the signal chain noise, so the resolution target is met only by oversampling/averaging or by a 20–24-bit converter; the budget shows the converter, not the amplifier, is the limiting element → specify a 20–24-bit delta-sigma.
• Layout: Kelvin (4-wire) bridge connection, symmetric trace lengths from the bridge to the in-amp, guard/shield around the high-impedance input, a solid ground plane, and no shared return between the bridge excitation and the ADC reference.

8. Calibration, Ratiometric Operation and Digital Correction

No analogue chain is accurate enough by itself; every serious sensor design includes a calibration and correction stage. Three techniques, in increasing order of effectiveness, cover almost every case.

Ratiometric operation. When the bridge and the ADC share the same excitation source, the excitation’s tolerance and drift cancel: the ADC’s reading is a ratio of two voltages that both scale with the excitation. This removes the biggest single error term (excitation tolerance, often 1–2%) at no cost, and it is the reason load-cell front ends are designed so that the ADC’s reference is derived from the bridge excitation. The condition is that the bridge’s output be measured differentially with respect to the same reference the ADC uses, and that the amplifier’s gain be stable (gain error is not cancelled by ratiometric operation).

Two-point calibration. Measure the chain with the sensor at zero load and at a known reference load; compute a gain and an offset correction and store them in non-volatile memory. This removes the sensor’s offset and span tolerance (typically 1–2% for a load cell’s span), the amplifier’s offset and gain errors, and the shunt/reference tolerances simultaneously. The calibration must be performed with the same excitation and reference used in operation, and the stored coefficients must be applied after the ADC’s raw conversion — the standard model is:

value = (raw − raw_zero) · K with K = reference_load / (raw_ref − raw_zero)

Multi-point and polynomial correction. When the sensor is nonlinear (thermocouples, RTDs with lead resistance, piezoelectric with charge leakage, strain gauges near their limit), a multi-point calibration with a piecewise-linear or polynomial fit reduces the error further. A thermocouple, for example, needs both cold-junction compensation and the NIST-type polynomial; the linear approximation loses several degrees at the range’s extremes.

/* Ratiometric two-point calibration with temperature-aware scaling.
   The ADC is assumed to be configured so that its full-scale code
   corresponds to the excitation voltage, which makes the reading a
   dimensionless ratio independent of the excitation's absolute value. */

typedef struct {
    int32_t raw_zero;     /* code with no load            */
    int32_t raw_ref;      /* code with the reference load */
    float   ref_value;    /* reference load in engineering units */
} cal_t;

static cal_t cal;

static inline float counts_to_units(const cal_t *c, int32_t raw)
{
    int32_t span = c->raw_ref - c->raw_zero;
    if (span == 0) return 0.0f;                    /* never calibrate with span = 0 */
    return (float)(raw - c->raw_zero) * (c->ref_value / (float)span);
}

/* Averaging: the signal is slow, so oversampling and averaging is almost
   free accuracy. Noise falls as sqrt(N) for uncorrelated samples. */
#define AVG_N 16

static int32_t read_filtered(int ch)
{
    int64_t acc = 0;
    for (int i = 0; i < AVG_N; ++i)
        acc += adc_read_raw(ch);
    return (int32_t)(acc / AVG_N);
}

/* Store the calibration in the last flash page, with a CRC, and check it
   at start-up: a corrupted calibration is worse than no calibration at
   all, because it silently shifts the readings. */
static bool cal_is_valid(const cal_t *c)
{
    return (c->raw_ref != c->raw_zero) && (c->raw_zero != 0);
}

Two further practical points. Oversampling and averaging is nearly free accuracy for slow signals: 16 samples reduce random noise by 4× (12 dB), and a moving average or a simple IIR filter handles the rest — but averaging does not remove offset, drift or the effects of a periodic interference, so it must be combined with calibration and, where mains-frequency interference is present, with synchronous (line-locked) sampling or a notch filter. And the calibration’s validity must be checked at start-up: a corrupted coefficient silently shifts every reading, which is far worse than an obvious failure. Storing a CRC with the coefficients and falling back to a conservative default (or refusing to report data) is the safer behaviour.

9. Verification and Testing

Signal-conditioning designs are verified with a small set of measurements that between them expose nearly every failure mode:

Test	What it validates	Typical criterion
Zero-input noise (short the input, 1000 samples)	Noise floor, interference, grounding	RMS noise ≤ the resolution limit divided by 3
Offset and drift with temperature	Amplifier offset, thermal EMF, reference drift	Within the error budget over the operating range
Two-point (or multi-point) calibration	Gain, linearity, sensor tolerance	Residual nonlinearity within half the accuracy target
Step response at the anti-alias filter’s input	Settling time, ringing, ADC driver stability	Settled within the sample interval for a full-scale step
Common-mode step (bridge excitation switching)	CMRR, settling, filter recovery	Reading recovers within one conversion after excitation turns on
Mains-frequency interference test	Filtering, shielding, grounding	Pickup below the resolution limit with the cable in the application
Full-range sweep against a reference instrument	End-to-end accuracy, including the ADC	Within the stated accuracy over the full range

Two of these deserve emphasis because they are so often skipped. First, the shorted-input noise test with the sensor connected but unloaded (rather than with a short across the amplifier’s input) is what reveals the interference the cable and the sensor pick up; a design that is quiet in the lab and noisy in the machine usually has this problem. Second, the common-mode step test: many bridges and many excitation schemes switch or modulate the excitation (to reduce power or to reject offsets), and the amplifier’s recovery from that step can take tens of milliseconds, which limits the achievable sample rate more than the ADC does. Measure it, do not assume it.

10. Reference Design Notes and Bring-Up Checklist

The circuit topology in this article is standard; what differs between a design that meets its accuracy target and one that misses it is the accumulated attention to the details surrounding that topology. The checklist below captures the items that most often turn up during bring-up, in the order in which they should be verified.

1. Excitation first, then offset. Measure the bridge’s excitation voltage at the bridge (not at the regulator) with the sensor connected; compute the full-scale output (excitation × sensitivity) and verify it against the expected value. A 5% error here propagates directly into the scale factor and is usually caused by a series element (a protection resistor, a long cable) rather than by the sensor.
2. Zero-input offset and its drift. Short the bridge input (or apply a known zero load) and record the offset at room temperature, then after a 30-minute warm-up, then in a temperature chamber if available. Compare the offset drift with the budget: an instrumentation amplifier with a 0.5 µV/°C drift contributes 1.5 µV across a 30 °C swing, which on a 20 mV full scale is 0.0075% — comfortably inside a 0.1% budget, whereas a poorly chosen op-amp front end can consume it entirely.
3. Noise at the output, with the input at zero. Measure with a bandwidth-limited meter or an FFT, and compare against the ADC’s LSB. If the peak-to-peak noise at the amplifier output exceeds a few LSBs of the ADC, no amount of oversampling will recover the required resolution, and the gain distribution (more gain before the ADC) is the usual correction.
4. Common-mode rejection in situ. Apply a common-mode step (for example by switching the excitation on and off, or by touching a common-mode source to the bridge’s reference) and observe the output disturbance. The CMRR specified in the data sheet is measured with ideal source impedances; an unmatched bridge resistance or a mismatched input filter destroys it in practice.
5. Linearity across the range. Apply at least five loads spanning the range, in both increasing and decreasing order, and compute the residuals against the fitted line. Hysteresis and non-linearity are separated by the direction of the sweep; a mechanical sensor often shows hysteresis that no electronic calibration can remove.
6. Temperature coefficients of the complete channel. Repeat a single load point at the two temperature extremes, and check that the span and offset changes are inside the budget. This test must include the reference and the ADC, not just the amplifier, because a ratiometric design moves the whole chain together while an absolute reference does not.
7. Antialiasing under real signals. Inject a signal above the filter’s cutoff (for example a fast transient or the switching frequency of a nearby converter) and confirm it does not appear as a spurious low-frequency reading; this is the test that reveals an antialiasing filter that exists on paper but not in the layout.

Recording these results in a table — parameter, measured value, budget, margin — turns the conditioning stage from an act of faith into a verifiable subsystem, and it makes the next revision’s changes provably better or worse rather than merely different.

11. Common Mistakes

• Choosing the amplifier by voltage noise alone: with a 350 Ω bridge and a high source impedance, current noise and bias current may dominate; match the amplifier noise type to the source impedance.
• Ignoring settling: an anti-alias filter that rings or a slow amplifier corrupts the multi-channel multiplexer settling and creates cross-channel error.
• Non-ratiometric excitation: a separate excitation and reference turns the supply drift into a gain error that no calibration removes.
• Asymmetric layout: mismatched source impedances and trace lengths convert common-mode noise into differential error; the in-amp’s CMRR is only as good as the layout symmetry.
• Over-specifying the amplifier while the ADC dominates: the error budget shows which stage limits the resolution; improving the wrong one wastes cost.
• Forgetting thermal EMF: at microvolt levels, a dissimilar-metal junction (connector, solder, trace) creates a temperature-dependent offset; use the same metal and keep the junctions isothermal.

12. FAQ

Q: How much gain should the in-amp provide? A: Enough to use most of the ADC’s input range (typically 70–90% of full scale) with headroom for offset and overrange, but not so much that the amplifier’s noise gain or CMRR error grows unnecessarily — split the gain between two stages if the total is high.

Q: Do I need a chopper amplifier? A: Only if the required DC accuracy is below the offset/drift of a standard in-amp over temperature; a chopper removes 1/f and offset but adds switching artefacts.

Q: How do I set the anti-alias corner? A: Below the Nyquist frequency with enough order to attenuate the sampling-rate content by the required amount; verify with the actual converter’s digital filter response.

Q: Does the reference matter as much as the amplifier? A: Often more, because a noisy reference multiplies the whole signal path; the reference must be low-noise, low-drift and filtered, and shared with the excitation for ratiometric designs.

13. Conclusion

Sensor signal conditioning is an error-budget exercise: know the sensor’s output and source impedance, excite it ratiometrically, pick the amplifier for the dominant error term, band-limit before the ADC, and prove the budget stage by stage. The data converter’s headline resolution means nothing if the front end injects more uncertainty than one LSB. Build the chain from the sensor outward, and the digitized number will mean exactly what the sensor measured.