1. Introduction — A Converter Is a Control Loop Before It Is a Power Stage

Engineers rarely lose a buck converter to insufficient inductance; they lose it to an unstable loop. The power stage — inductor, output capacitor, switches and load — has a transfer function with a double pole from the LC filter, a zero/ESR from the capacitor, and a sample-and-hold delay from the modulator. The error amplifier and its compensation network must shape the loop so that the crossover frequency is comfortably below the switching frequency, the phase margin is 45–60°, and the gain is high enough at DC to regulate the output within tolerance. This guide covers the power-stage model, the pole/zero arithmetic, the Type II and Type III compensators and when each is required, the crossover-frequency selection rule, the capacitor ESR and load-range influence, the current-mode vs voltage-mode difference, an S-domain design procedure with a complete worked example, and the measurement technique that proves the design (the Bode plot via a perturbation injection). It complements the buck converter and feedback loop compensation calculator pages on this site.

2. The Power Stage Model

For a voltage-mode buck operating in continuous conduction, the control-to-output transfer function is approximately:

Gvd(s) = Vin · (1 + s/ω_esr) / (1 + s/(Q·ω_0) + s²/ω_0²)

with the LC corner ω_0 = 1/√(L·C_out), the ESR zero ω_esr = 1/(R_esr·C_out), and the quality factor Q = 1/( ω_0·(L/(R_load)) + R_ds·√(C_out/L) ) in the simplified form. The salient features: a flat gain at low frequency, a resonance at ω_0 where the phase drops sharply toward −180°, and an ESR zero that lifts the phase back. High-ESR electrolytic capacitors push that zero low and help stability; low-ESR ceramics and polymer capacitors push it up out of the useful band and make the double pole dominate — which is exactly why “replacing the output cap with a better one” can turn a stable converter into an oscillator. The gain also moves with the input voltage and the load current: the DC gain ∝ Vin, and the load resistance moves Q and the resonance, so the design must be checked at the extremes of the operating envelope, not just at nominal.

3. Poles, Zeros and What the Compensation Must Do

Network	Elements	Provides	Typical use
Type I (integrator)	1 pole at origin	−20 dB/dec, 90° lag	Rarely sufficient alone
Type II	1 pole at origin + 1 pole + 1 zero	−20 dB/dec, up to ~90° phase boost	Current-mode converters, low-ESR output caps
Type III	1 pole at origin + 2 poles + 2 zeros	−20 dB/dec at crossover, up to ~180° boost	Voltage-mode with LC double pole

The compensation’s job is to cancel the phase loss at the crossover frequency: the loop gain T(s) = Gc(s)·Gvd(s)·H(s) should cross unity with a slope of −20 dB/dec (or −1) and a phase margin of at least 45°. For a voltage-mode buck with the LC double pole (−180° of lag) plus the modulator delay, a Type III compensator with two zeros placed near (or slightly below) ω_0 is usually needed. For a current-mode converter the inductor current is controlled directly, the power stage behaves as a single-pole system above the LC resonance, and a Type II compensator suffices — that simplification is the main practical advantage of current-mode control. Placement rules: put the compensator zeros at or slightly below the LC corner to recover the phase, put the high-frequency poles above the crossover to roll off the gain and reject switching noise, and keep the crossover well below f_sw (1/10 to 1/6 of f_sw is a common starting point, often 1/10 for voltage-mode and 1/6 for current-mode).

4. Choosing the Crossover Frequency

The crossover frequency f_c is the single most consequential choice. Higher f_c gives faster transient response and lower output impedance over the band, but it reduces the phase margin because the modulator’s sampling and propagation delay add phase lag proportional to frequency, and it pushes the design toward the switching ripple. The practical rules:

• f_c ≤ f_sw/10 for voltage-mode (the sampling delay and the LC resonance limit the achievable bandwidth).
• f_c ≤ f_sw/6 for current-mode (the single-pole behaviour permits more bandwidth).
• f_c should be high enough to meet the transient load-step requirement: for a load step ΔI, the peak deviation is roughly Δi/(2π·f_c·C_out) — solve for f_c from the allowed voltage deviation.
• Keep f_c at least 5× below the ESR zero if you need the compensator’s phase boost, and above the LC corner where the double pole has already done its damage.

The transient requirement and the phase-margin requirement pull in opposite directions; the design process is to pick the lowest f_c that meets the transient specs with margin, then verify the phase margin at all corners. The relevant switching and modulation frequencies and the power stage’s operating point can be confirmed with the switching frequency calculator and the converter’s inductor/capacitor operating values with the buck converter calculator before committing to the compensation.

5. Type II and Type III Networks in Practice

A Type II compensator around a transconductance or voltage-feedback error amplifier is a resistor with two capacitors to ground (or the op-amp equivalent): one capacitor sets the pole at the origin (integrator), the series R-C sets the zero, and a second small capacitor sets the high-frequency pole. The transfer function is:

Gc(s) = (ω_mid/s) · (1 + s/ω_z) / (1 + s/ω_p)

A Type III adds a second zero and a second pole, giving the extra phase boost to carry the loop through an LC double pole. Design sequence: (1) compute the power-stage poles/zeros; (2) choose f_c; (3) place the Type III zeros at f_0 (or f_0/√2) and the poles above f_c (one at the ESR zero if it is low, one at ~f_sw/2 for noise); (4) scale the gain so that |T(j·2π·f_c)| = 1; (5) verify the phase margin across load, Vin and temperature. Two practical cautions: the modulator gain (PWM ramp amplitude) enters the loop gain directly and is often wrong in a first-pass calculation, so measure it; and the op-amp’s own gain-bandwidth product must be far above the crossover, or the amplifier’s own pole eats the phase margin. A code-side sanity check of the computed component values (resistor dividers and parallel combinations in the feedback network) is straightforward with the resistor parallel calculator when a network needs to be realized from standard values.

6. Voltage-Mode vs Current-Mode Compensation

Aspect	Voltage mode	Current mode
Power-stage order	Double pole (2nd order)	Single pole above resonance
Compensator needed	Type III typically	Type II typically
Achievable f_c	f_sw/10	f_sw/6
Line feed-forward	Poor without extra ramp	Better (inductor current is controlled)
Sensitivity	LC and load dependent	Sub-harmonic oscillation above 50% duty, needs slope comp.

Current-mode control linearizes the inductor into a controlled current source, so the output capacitor and load form the dominant pole and a Type II compensator is normally enough. The price is the sub-harmonic oscillation when the duty cycle exceeds 50% without adequate slope compensation, and a greater sensitivity to the current-sense noise. Voltage-mode is simpler conceptually and immune to sub-harmonic issues, but demands the Type III network and yields less bandwidth. The choice is usually dictated by the controller IC (integrated compensators are almost always current-mode-optimized) and by the required transient performance.

7. Worked Example — 12 V to 3.3 V, 5 A, 500 kHz Voltage-Mode Buck

Target: 3.3 V at 5 A, Vin 12 V, f_sw 500 kHz, L = 4.7 µH, C_out = 100 µF ceramic (ESR 3 mΩ), transient spec 3.3 V ±5% for a 2 A load step.

• LC corner: f_0 = 1/(2π√(4.7 µH × 100 µF)) = 1/(2π × 21.7 µs) ≈ 7.3 kHz. The double pole is low relative to f_sw.
• ESR zero: f_esr = 1/(2π × 3 mΩ × 100 µF) ≈ 530 kHz — above the intended crossover, so it gives no useful phase boost; this is the classic ceramic-capacitor case requiring Type III.
• Crossover: voltage-mode rule f_c ≤ f_sw/10 = 50 kHz; take 45 kHz for margin. Transient check: ΔV ≈ Δi/(2π·f_c·C) = 2 A/(2π × 45 kHz × 100 µF) ≈ 71 mV, well inside the 165 mV (±5%) allowance — so the loop can be slower if needed.
• Type III placement: zeros at f_0 ≈ 7.3 kHz (recover the double-pole phase), one high-frequency pole at ~f_esr/2 to flatten the ESR zero’s effect, one at ~f_sw/2 = 250 kHz for switching-noise rejection.
• Gain scaling: set the mid-band gain so |T(jω_c)| = 1; the modulator gain (Vin/V_ramp) must be measured or taken from the datasheet (e.g. V_ramp = 1 V → Gm = 12). Verify by simulation and then measure.
• Corner check: re-evaluate at Vin = 10.8 V and 13.2 V (the DC gain ∝ Vin changes ±10%) and at light load where Q rises; confirm phase margin ≥ 45° at every corner and no peaking above +6 dB.
• Measurement: inject a small signal across a 10 Ω resistor in the feedback path (or use a dedicated injection transformer) and sweep 100 Hz–500 kHz with a network analyzer or a FRA; measure the crossover and phase margin on the real board — the fastest way to catch a simulation-only design.

8. From Analogue to Digital Compensation

When the controller is a microcontroller or a DSP rather than a dedicated analogue IC, the same loop-shaping problem is solved with a difference equation. The conversion is mechanical once the analogue network’s transfer function is known: a Type II compensator, for example, is discretised with the bilinear transform (Tustin) or the pole-zero matching method, and the resulting coefficients are implemented as a direct-form II transposed biquad. Three practical differences from the analogue case deserve attention. First, the sampling rate matters: the digital loop introduces a delay of one to one-and-a-half sampling periods, and that delay adds phase lag at the crossover frequency (about 20° per sampling period at f_c = f_s/10), which must be included in the phase margin budget — the analogue design’s phase margin must be reduced accordingly, or the crossover lowered. Second, the ADC’s quantisation and the computation’s word length set a noise floor and can cause limit cycles; a 12-bit ADC with a 1.65 V reference gives about 400 µV per LSB, and if the output voltage ripple requirement is a few millivolts, the loop’s error signal has only a handful of LSBs of resolution at steady state, which is why digital loops for tight regulation often use a higher-resolution ADC or a dithered PWM. Third, the duty-cycle resolution limits the smallest output correction: an 8-bit PWM at 500 kHz has a 7.8 ns resolution, which at 12 V input corresponds to roughly 10 mV of output step — the same order as the acceptable ripple, so the PWM resolution becomes part of the regulation budget.

/* Discrete Type II compensator, direct-form II transposed.
   Designed in the continuous domain for f_c = 50 kHz, PM = 60 deg,
   a zero at 5 kHz and a pole at 200 kHz; Tustin-discretised at
   fs = 500 kHz. Coefficients are Q15 fixed point here for clarity. */

typedef struct {
    float b0, b1, b2;   /* numerator   */
    float a1, a2;       /* denominator (a0 normalised to 1) */
    float z1, z2;       /* state */
    float out_max;      /* anti-windup clamp */
} comp_t;

static inline float comp_step(comp_t *c, float err)
{
    /* Direct-form II transposed: one multiply-accumulate chain, low
       coefficient sensitivity, and only two state variables. */
    float y  = c->b0 * err + c->z1;
    c->z1    = c->b1 * err - c->a1 * y + c->z2;
    c->z2    = c->b2 * err - c->a2 * y;

    /* Clamp before it reaches the PWM; the clamp must be inside the
       loop (not after it) so that the state variables do not wind up. */
    if (y >  c->out_max) y =  c->out_max;
    if (y < -c->out_max) y = -c->out_max;
    return y;
}

/* Verify the discrete design before flashing it: compute the closed-loop
   response from the discretised plant and the compensator, and check that
   the crossover and phase margin survive the digital delay. */

The anti-windup clamp is not optional in a digital compensator: when the output saturates during a load transient or a start-up ramp, the integrator’s state keeps accumulating and the loop then takes a long time to recover, which shows up as an overshoot after the transient has ended. Clamping the internal state (or freezing the integrator while saturated) is the standard cure. It is also worth simulating the complete discrete loop — plant, ADC quantiser, delay, compensator and PWM quantiser — before building hardware; a five-line Python or spreadsheet model of the discrete loop catches most start-up and transient problems that a continuous-domain design ignores.

9. Practical Design Procedure, Measurement and Verification

A repeatable sequence that works for both analogue and digital designs:

1. Characterise the plant. Measure the power stage’s gain and phase versus frequency with a network analyser or a frequency-response analyser (a small signal injected into the feedback path with the loop opened at a suitable point). Datasheet parameters — inductor DCR, capacitor ESR, MOSFET RDS(on) — give a first estimate, but the measured plant usually differs by several dB because of parasitics and the load’s own impedance.
2. Choose the crossover frequency from the switching frequency (typically f_s/10 to f_s/20) and check both the Nyquist constraint of the sampling and the worst-case load (the load’s own dynamics can add phase lag).
3. Design the compensation for the required phase margin at the crossover, placing zeros to cancel the dominant plant poles (or to flatten the gain) and a high-frequency pole to attenuate the switching ripple.
4. Simulate the closed loop over the operating envelope: minimum and maximum input voltage, no load and full load (including the load’s capacitance, which changes the plant), and at temperature extremes if the design is marginal.
5. Verify on hardware with the loop-gain measurement repeated, a load step at several operating points, a line step and a start-up capture; check the transient’s settling time and overshoot against the specification, and re-measure at the temperature extremes.

Two measurement traps are common. First, injecting a signal into a closed loop requires a suitable injection point (a small resistor in the feedback path, or the summing node of the error amplifier); injecting across the output capacitor instead measures something else entirely. Second, the load connected during the measurement changes the plant: measuring with a purely resistive load and then operating into a constant-power load (which has a negative input impedance and can destabilise the loop) is one of the classic ways to pass the bench test and fail in the application. A constant-power load’s negative resistance reduces the damping of the output filter’s resonance, and at light load the converter’s own losses may be the only damping left — which is why load-step testing must include the light-load and the constant-power cases, not only the resistive full-load case.

10. Load Transients, the Output Filter and Parallel Operation

The compensated loop does not act alone: the output capacitance, the load’s own input filter and any parallel converters all take part, and three interactions deserve explicit attention.

Load transient, not crossover, is what the user sees. The crossover frequency sets how fast the loop can react, but the initial voltage excursion after a load step is set by the output capacitance and the ESL of the capacitor-plus-layout path before the loop responds at all. The first-order estimate is a charge-balance calculation: ΔV ≈ (ΔI · t_response) / C_out, where t_response is roughly 1/(2π f_c). A 5 A step with f_c = 50 kHz and 100 µF gives (5 × 3.2 µs)/100 µF ≈ 160 mV of excursion, ignoring ESR, ESL and the ramp of the inductor current — which is why the measured transient is typically larger than the calculation and why the capacitor’s ESR and the via inductance matter as much as the capacitance value. Increasing C_out reduces the excursion linearly but also pushes the power-stage pole down, which lowers the achievable crossover for the same compensation; the loop and the capacitor bank must be designed together.

The load’s input filter can destabilise the converter. A converter feeding another converter presents a negative input impedance (−V²/P) that can resonate with the intervening LC network and produce oscillation at a frequency unrelated to either loop. The practical fixes are to damp the intermediate filter (an RC or a lossy ferrite, not a pure LC), to keep f_c of the upstream converter well below the resonant frequency of the downstream filter, and to add a feed-forward term where the controller supports it.

Parallel and phase-shedding converters. When two converters share a load, their loops interact through the common output node. The robust arrangement is a single master reference with the slaves tracking it (current-mode sharing), with the compensation designed for the worst-case number of active phases rather than for one. Phase shedding changes the effective power-stage gain and the output pole, so the compensation must remain stable across the whole phase count — the reason many designs specify a worst-case crossover margin of 45° or better across all modes.

11. Common Mistakes

• Ignoring the modulator gain: the PWM ramp amplitude scales the loop gain directly; assuming 1 V/V when the part is 0.5 V/V doubles the actual crossover and erases the margin.
• Upgrading to low-ESR capacitors without re-compensating: removing the helpful ESR zero destabilizes a marginally compensated loop.
• Designing only at nominal load: the light-load Q rises and the phase margin falls; check the whole load range.
• Forgetting the error amplifier’s own pole: an op-amp with a modest GBW adds lag at the crossover; the amplifier must be much faster than f_c.
• Crossover too close to f_sw: the sampling delay and the ripple take over; keep f_c ≤ f_sw/10 (voltage-mode) or f_sw/6 (current-mode).
• Never measuring the loop: a simulation-only compensation is unverified; inject and measure the Bode plot on hardware.

12. FAQ

Q: How do I know if I need Type II or Type III? A: Count the phase lag at the desired crossover. A voltage-mode LC double pole needs the extra zero → Type III; a current-mode single-pole stage needs only one zero → Type II.

Q: What phase margin should I aim for? A: 45° is the accepted minimum, 50–60° gives good transient damping without excessive settling time; below 40° the step response rings noticeably.

Q: Can I just use a large output capacitor and skip compensation? A: No. A larger C lowers f_0 and slows the loop, but the double pole still needs phase compensation; the capacitor changes the placement, not the need.

Q: Why does the converter oscillate only at light load? A: At light load the damping falls (Q rises) and the resonance peaks, so a loop with marginal phase margin becomes unstable; the compensation must cover the worst-case Q.

13. Conclusion

Loop compensation is applied control theory on a power stage: model the poles and zeros, place the compensator zeros to recover the phase at the crossover, scale the gain to unity at f_c, and verify the phase margin across every corner of load, line and temperature. Choose the crossover from the transient requirement and the switching-frequency rule, prefer current-mode’s Type II when the controller allows, and always measure the loop on hardware. A converter with a properly compensated loop regulates cleanly through every transient and stays quiet for its whole life.