1. Introduction — The Clock Is a Signal, Not a Fact

Every synchronous digital system assumes edges arrive at a known instant. The clock tree is what makes that assumption true, and it is also where most “intermittent, only on one board, only when warm” failures originate. A clock is not a square wave but an analog signal with rise time, amplitude, duty-cycle error, phase noise and jitter; the tree that distributes it — oscillators, PLLs, buffers, dividers, multiplexers and the PCB traces between them — determines whether the timing budget holds. This guide covers the oscillator/PLL architecture and the multiplication arithmetic, the sources and taxonomy of jitter, how to build and verify a jitter budget, the layout and termination of clock traces, and the closely related problem of safely transferring data across clock domains that are not perfectly related. It complements the FPGA timing constraints and digital logic design guides on this site.

2. Architecture: Reference, PLL, Dividers, Distribution

A typical clock tree starts with a reference (a crystal oscillator, a TCXO for tighter stability, or a MEMS oscillator), multiplies it in a PLL to the system frequency, then divides and distributes. The PLL’s output frequency is:

f_vco = f_ref · (N/M); f_out = f_vco / P

where M is the input (pre-)divider, N the feedback divider, and P the post-divider. The design constraints are: (a) f_vco must stay inside the VCO’s specified range (typically 100 MHz–1 GHz for an MCU PLL), which is why the M/N/P combination is chosen to land the VCO in the middle of its band; (b) the phase detector comparison frequency f_ref/M must be low enough for the loop filter but high enough to keep the loop stable and the in-band phase noise low; (c) the reference’s phase noise is multiplied by 20·log10(N/M) dB inside the loop bandwidth — a 20 MHz reference at 10 ppm phase noise becomes 40 dB worse if the multiplication ratio is 100. The practical rule: keep the multiplication ratio modest, keep the VCO mid-band, and prefer a higher reference frequency when the multiplication ratio would otherwise be large. Verifying the intended frequencies and the resulting timer/modulation rates is a natural place to use the switching frequency calculator as a quick check of period/frequency relationships in the clock-derived timing.

3. Jitter: Taxonomy, Sources, Propagation

Jitter type	Definition	Dominant source	How it accumulates
Period jitter	Deviation of one period from the ideal	VCO noise, supply noise	Measured cycle to cycle
Cycle-to-cycle (C2C)	Difference between adjacent periods	Broadband noise	Does not accumulate over N cycles
Long-term / N-cycle	Deviation of an N-cycle interval	1/f noise, wander	Grows as √N (random) or N (drift)
Deterministic (DJ)	Bounded, repeatable	Supply ripple, crosstalk, duty distortion	Adds linearly, hard limit on eye
Random (RJ)	Gaussian, unbounded	Thermal, shot noise	Adds as RSS
Total (TJ)	DJ + n·RJ	Both	TJ = DJ + Q(BER)·RJ

In a system, the total jitter is the RSS of the contributors: the reference oscillator, the PLL’s own VCO and loop noise (low-frequency multiplied reference noise inside the loop bandwidth, high-frequency VCO noise outside), the distribution buffers, the crosstalk from adjacent switching signals, and the supply noise that modulates the buffer’s threshold. The reason jitter budgets fail is almost never the oscillator’s headline spec — it is a 100 mV supply ripple on a clock buffer, a clock trace running parallel to a switching node for 10 mm, or a PLL whose loop filter sees a noisy supply. Supply-induced jitter is deterministic and therefore directly reducible: filter and decouple the clock buffer’s supply heavily (the same low-impedance, high-frequency decoupling discipline as any fast digital rail) and keep switching return currents out of the clock’s ground reference. The decoupling network for the clock and PLL supply can be sized with the decoupling capacitor calculator, targeting the impedance at the clock’s edge rate and the PLL’s loop bandwidth.

4. Building and Verifying a Jitter Budget

Jitter budgets are built by stage and verified in the time domain, not by summing datasheet numbers blindly. The procedure:

• Define the requirement in the units of the interface: a serial link specifies a total jitter (TJ) at a bit-error rate (typically 1e-12), an ADC clock specifies an aperture jitter (because SNR degrades with clock jitter), and a synchronous bus specifies setup/hold margins. Convert everything to a common unit (ps rms or ps p-p) before adding.
• Tabulate each contributor in the same units, separating random (RSS) from deterministic (linear sum).
• Add the margin (typically 20–30% of the total) and compare to the requirement. If the budget fails, attack the largest deterministic term first — it is the cheapest to remove.
• Verify by measurement: a phase-noise analyzer or a real-time scope with a jitter/timestamp option. Remember that the measurement bandwidth defines the number: an RJ measured over 100 kHz–10 MHz is not comparable with one measured over 10 Hz–1 MHz.
• Check the corners: jitter rises at temperature extremes and at supply-voltage extremes; the budget must hold at the worst corner, not the typical.

A useful relation for ADC clocks: the SNR limit from clock jitter is SNR = −20·log10(2π·f_in·t_jitter). At a 10 MHz input and 1 ps rms jitter, the limit is about 84 dB; at 10 ps rms it drops to 64 dB — which is why a converter claiming 90 dB at high input frequency needs a jitter cleaner, not a better converter.

5. Distribution: Layout, Termination, Skew

Once the clock is generated it must arrive everywhere with matched delay and clean edges. Practical rules: (a) route clocks as controlled-impedance traces (50 Ω) with a solid reference plane and no plane splits under them; (b) series-terminate at the source (a 22–33 Ω resistor at the driver) to damp the reflection and control the edge rate — faster is not better, because the fast edge couples more crosstalk; (c) match the trace lengths between the clock and the devices that must be synchronous, keeping the skew inside the setup/hold margin (the skew budget is usually a fraction of the period, e.g. ≤5–10%); (d) never route a clock parallel to a switching node or a high-speed data bus for a long distance — keep ≥3× the trace width separation, or use a ground guard trace; (e) if the clock must cross a connector or leave the board, use a differential clock (LVDS/LVPECL) for common-mode rejection. The clock tree’s skew and the flip-flop’s setup/hold times are what determine the maximum usable frequency; a clean 100 MHz clock with 2 ns of uncontrolled skew is worse than a jittery one with none.

6. Clock Domain Crossing (CDC)

When data moves between two clock domains, the receiving flip-flop’s input can change during its setup/hold window — the metastability problem. The standard mitigations:

Structure	Use	Latency	Notes
Two-flop synchronizer	Single-bit level/flag	2–3 cycles	MTBF from the flop’s settling time; keep both flops close
Handshake (req/ack)	Multi-bit or slow signals	4+ cycles	Safe for buses; adds handshake latency
Asynchronous FIFO	Streaming data	FIFO depth	Gray-coded pointers; the workhorse for CDC streams
Mux/pulse synchronizer	Single pulse events	2 cycles	Pulse must be wider than the destination period

The reliability metric is the mean time between failures from metastability: MTBF = e^(t_r/τ) / (T_0 · f_clk · f_data), where t_r is the settling time allowed (one destination period minus the setup time), τ and T_0 are the flop’s metastability constants (from the vendor’s library), f_clk the destination frequency and f_data the data rate. In an FPGA the vendor’s timing analysis can report the MTBF for a given synchronizer; in an ASIC/MCU the rule of thumb is that two flip-flops with a full period of settling give an MTBF in the millions of years, and three flip-flops are used when the clock is fast and the flop is slow. The absolute rule is never to use a multi-bit signal through independent per-bit synchronizers — the bits can be captured in different cycles and the destination sees a combination that never existed. Either use a Gray-coded counter (one bit changes at a time), a handshake, or an async FIFO.

7. Worked Example — 25 MHz Reference to 200 MHz System Clock with an ADC

Target: a 25 MHz crystal (±20 ppm) drives a PLL to a 200 MHz core clock; an ADC is clocked at 100 MHz and samples a 10 MHz input; the clock-to-ADC trace is 15 mm; total jitter budget for 12-bit SNR ≥ 70 dB at 10 MHz.

• PLL: 200/25 = 8 → choose M = 1, N = 64, P = 8 so f_vco = 1.6 GHz (mid-band for a typical VCO range) with a 25 MHz phase detector. The reference noise is multiplied by 20·log10(8) ≈ 18 dB inside the loop.
• Jitter requirement: SNR = −20·log10(2π·10 MHz·t_j) = 70 dB → 2π·10 MHz·t_j = 10^(−3.5) → t_j ≤ 3.16e-4/(6.28e7) ≈ 5.0 ps rms. That is the total budget for the ADC clock.
• Budget: reference 0.5 ps, PLL VCO 1.2 ps, distribution buffer 0.6 ps, supply-induced 2.0 ps, crosstalk 1.0 ps → RSS = √(0.25 + 1.44 + 0.36 + 4.0 + 1.0) ≈ 2.6 ps rms, leaving almost 2× margin. The deterministic supply term is the largest; the clock decoupling network is sized with the decoupling calculator to keep the rail impedance low at the edge rate.
• Distribution: 50 Ω microstrip, 25 Ω series termination at the buffer, length-matched to ±0.5 mm to the ADC, ≥3× width separation from the data bus, and no plane splits under the trace.
• CDC: the ADC data is captured in the 100 MHz domain and read by the 200 MHz core; the two clocks are synchronous (same PLL, integer ratio 2:1), so a simple synchronous capture with a valid pipeline is sufficient — no two-flop synchronizer is required because the domains are related. If the ADC ran on its own 98 MHz clock, the design would need an async FIFO for the data bus.
• Verification: measure the ADC clock’s phase noise, integrate it 10 kHz–20 MHz, and confirm the rms jitter is inside the 5.0 ps budget; measure the SNR with a 10 MHz input to confirm the end-to-end result.

8. Glitch-Free Clock Switching and Clock Monitoring

Systems that support multiple clock sources — a crystal for normal operation, an internal RC oscillator for start-up or fallback, an external reference for synchronisation — need a glitch-free mux. A glitch on the system clock during a switch resets or corrupts every synchronous block in the design, and the failure is intermittent, load-dependent and extremely difficult to reproduce. The requirement is simple to state: at the moment of switching, the new clock must be running and stable, the old clock must be stopped cleanly after the last complete pulse, and neither a runt pulse nor a truncated pulse may reach the downstream logic. The implementation is a pair of synchroniser-plus-gate circuits with a handshake, so that the two clocks are never enabled simultaneously:

// Glitch-free two-input clock mux (Verilog, for illustration).
// Each branch passes its clock only when the other branch is confirmed
// disabled; the two enables are mutually exclusive through the handshake.
module clk_mux_glitchfree (
    input  wire clk_a, clk_b,
    input  wire rst_n,
    input  wire sel,        // 0 = a, 1 = b
    output wire clk_out
);
    reg a_en_a, b_en_b, a_en_sync_b, b_en_sync_a;

    // Enable path for A: request is granted once B is confirmed off.
    always @(posedge clk_a or negedge rst_n)
        if (!rst_n)            a_en_a <= 1'b0;
        else                    a_en_a <= ~sel & ~b_en_sync_a;

    always @(posedge clk_b or negedge rst_n)
        if (!rst_n)            b_en_sync_a <= 1'b0;
        else                    b_en_sync_a <= a_en_a;   // 2-FF sync in B domain

    always @(posedge clk_b or negedge rst_n)
        if (!rst_n)            b_en_b <= 1'b0;
        else                    b_en_b <=  sel & ~a_en_sync_b;

    always @(posedge clk_a or negedge rst_n)
        if (!rst_n)            a_en_sync_b <= 1'b0;
        else                    a_en_sync_b <= b_en_b;

    // The AND gates guarantee a full-width pulse: the enable only changes
    // while the corresponding clock is low.
    assign clk_out = (clk_a & a_en_a) | (clk_b & b_en_b);
endmodule

Clock monitoring is the complement of switching: a loss-of-lock or loss-of-signal detector on the reference and on the PLL’s feedback path, with a defined response (switch to the backup source, assert a safe state, or flag the fault). The detector’s own delay defines how long the system runs on a bad clock, so it must be fast enough to prevent the downstream logic from seeing out-of-specification frequencies. For safety-relevant designs the monitor’s response is specified in the functional safety concept, and the monitor itself must be testable — a monitor that cannot be provoked cannot be trusted.

9. Spread-Spectrum Clocking and EMI

Modulating the clock frequency over a small range (typically −0.5% to −2%, with a modulation rate of 30–60 kHz) spreads the clock’s harmonics over a band and reduces the peak spectral amplitude measured by an EMI receiver. A 1% spread at 100 MHz moves energy over 1 MHz of bandwidth; the peak reduction for a triangular modulation is approximately:

ΔPeak ≈ 10 · log10( Δf_spread / B_RBW ) for Δf_spread >> B_RBW (approximate; a triangular profile with realistic rise times gives a few dB less)

The trade-offs are real and must be assessed per interface. Spread-spectrum clocking adds frequency modulation, which appears as additional jitter to any synchronous interface using that clock: the peak-to-peak period deviation equals the spread percentage (1% of a 100 MHz period is 100 ps of period change), and a receiver’s timing margin must absorb it. Interfaces with their own clock recovery (SSC-capable SerDes, USB, SATA, PCIe in SSC mode) are designed to tolerate defined amounts of it; interfaces that assume a fixed-frequency clock (an ADC’s aperture jitter budget, a synchronous serial link, a frequency counter) are not. Down-conversion in a radio is another consideration: spreading the clock of a digital block reduces the peak of a spur but smears it into noise across the band, which can raise the noise floor where a single narrow spur used to be. The engineering discipline is the same as everywhere else in this domain: define the sensitivity of each interface to frequency modulation, choose the spread and modulation rate to satisfy the tightest one, and verify against the actual EMI limit with the modulation enabled and disabled.

10. Measuring Jitter Correctly: Instruments, Methods and Traps

Jitter numbers are easy to obtain and easy to get wrong, and an unqualified jitter figure is worse than none at all. The three instruments in common use measure different things, and the conversion between them is where most budget errors occur.

Instrument	Measures	Strength	Trap
Real-time oscilloscope (TIE)	Time-interval error of edge crossings versus an ideal clock	Direct, shows the time-domain behaviour, reveals periodic/systematic components	Trigger and scope noise (a 1 GHz, 1 mVrms front end contributes picoseconds) enter the measurement; a 100 MHz clock measured on a 500 MHz probe is dominated by instrument jitter
Phase-noise analyser (spectral)	Single-sideband phase noise L(f) versus offset	Separates random from spurious, integrates into any band of interest	Requires a clean reference; the analyser’s own floor must be well below the DUT’s
Jitter analyser / BERT	RMS and peak-to-peak jitter, bathtub curve	Automatic integration bandwidths, BER-linked figures of merit	The integration band is chosen by the instrument; a different band gives a different number

The essential discipline is to state the integration bandwidth with every RMS figure. A phase-noise trace can be converted to RMS jitter in a given band by integrating the phase noise and converting to the time domain:

import math

def rms_jitter_fs(phase_noise_MHz, f0_MHz, f_low_Hz=1e3, f_high_Hz=1e7):
    """RMS jitter from a phase-noise spectrum.
    phase_noise_MHz: list of (offset_Hz, L_dBc_per_Hz)
    f0_MHz: carrier frequency
    """
    total = 0.0
    pts = sorted(phase_noise_MHz)
    for (f1, l1), (f2, l2) in zip(pts, pts[1:]):
        # integrate over each segment, skipping ranges outside the band
        a, b = max(f1, f_low_Hz), min(f2, f_high_Hz)
        if b <= a:
            continue
        l_avg = (l1 + l2) / 2.0
        lin = 10 ** (l_avg / 10.0)
        total += lin * (b - a)          # integral of the SSB power density

    phase_rms = math.sqrt(2.0 * total)  # rad
    t_0 = 1.0 / (f0_MHz * 1e6)
    return phase_rms / (2 * math.pi) / t_0 * 1e15   # femtoseconds

# Dual-band reading is the honest way to report the result:
#   a narrow band (1 kHz - 5 MHz) for the loop-relevant jitter,
#   a wide band (1 kHz - 20 MHz) for the serial-link budget.

Three traps recur in practice. First, measuring the clock at the source pin rather than at the receiver's input ignores the distribution network's contribution — the same clock measured at the two points can differ by more than the oscillator's own jitter. Second, using a single-number "jitter" specification without the band (a part claiming 0.5 ps where the integration band turns out to be 12 kHz–20 MHz is not comparable to one claiming 1 ps over 100 Hz–1 MHz). Third, treating spurs as random jitter: a strong periodic component at the reference frequency will not average away with repeated measurements, and it originates from an impedance mismatch or a bypassing problem that no amount of cleaning up in firmware will fix. For a practical bench setup, the honest procedure is to measure the phase noise where possible, to verify at least one point on the time-domain TIE with a low-noise scope, and to record both the value and the band in the design file so that the number can be compared later.

11. Common Mistakes

• Assuming the oscillator spec is the system jitter: the PLL, buffers, supply and crosstalk usually dominate; the budget must include them.
• Route the clock next to a switching node: deterministic crosstalk jitter that no oscillator upgrade can fix; reroute or shield.
• Uncontrolled source termination: reflections double the edges and add jitter; always series-terminate trace clocks.
• Multi-bit CDC without Gray/handshake/FIFO: the destination can capture a transient combination and produce a "phantom" value.
• Loop filter on a noisy rail: the PLL's supply noise modulates the VCO directly; decouple and filter the PLL supply separately.
• Comparing jitter numbers measured over different bandwidths: an RJ figure is meaningless without the integration band; always state the band.

12. FAQ

Q: How much jitter is acceptable? A: It depends on the interface: derive the limit from the SNR (ADC), the eye (serial link) or the setup/hold margin (synchronous bus), then allocate the budget with 20–30% margin.

Q: Do I need a jitter cleaner? A: Only if the derived requirement is below what the PLL + reference + distribution can deliver; a cleaner buys ps-level rms but only helps when the dominant term is the reference/PLL, not supply-induced deterministic jitter.

Q: How do I know a CDC is safe? A: Use a recognized structure (two-flop synchronizer for single bits, handshake or async FIFO for buses), constrain it in the timing tool, and check the reported MTBF; never synchronize multi-bit buses per bit.

Q: Does a faster clock edge help timing? A: No — faster edges worsen crosstalk, ringing and EMI; control the edge rate with series termination and route with a solid reference plane.

13. Conclusion

The clock tree is an analog signal chain distributing a timing reference. Choose the PLL ratios to keep the VCO mid-band and the multiplication modest, build a jitter budget in the interface's own units and verify it on hardware, distribute with controlled impedance and matched skew, defend the clock's supply and ground from switching noise, and cross clock domains only with structures whose MTBF you can compute. Do that and the system's timing margin belongs to the design, not to luck.