1. Introduction — When a Trace Is a Transmission Line

Above a few hundred MHz (or with sub-nanosecond edges), a PCB trace is no longer a wire — it is a transmission line whose characteristic impedance Z0 is set by geometry and material: the trace width, the dielectric thickness to the reference plane, the dielectric constant (Dk, aka Er) of the laminate, and the presence of neighboring ground/power pours. If the impedance of the trace does not match the source impedance (the driver) and the load (the receiver, often 50 Ω or 100 Ω differential), each edge reflects energy: ringing on the waveform, ISI (inter-symbol interference), EMI, and failed timing margins. Impedance control is the systematic discipline of designing the stackup, the trace dimensions and the manufacturing tolerances so that every signal trace lands within its impedance spec. This guide covers the microstrip vs stripline trade, the computed Z0 formulas, stackup design with the reference planes, the differential-pair math, tolerance budgeting against the fab, and the return-path discipline that supports the whole system. It complements the high-speed routing and signal-integrity guides on this site.

2. Microstrip vs Stripline

Property	Microstrip (outer layer)	Stripline (inner layer)
Cross-section	Trace on surface, reference plane below	Trace between two reference planes
Dk exposure	Partly air (Dk≈1)	Fully embedded (Dk of laminate)
Effective Dk	Lower (faster edges, wider traces)	Higher (narrower traces for same Z0)
Signal integrity	More crosstalk/EMI, no top shield	Better isolation, both planes shield
Manufacturing tolerance	Width control matters most	Dielectric thickness control matters
Usage	RF/antenna edges, low-cost boards	DDR/high-speed buses, controlled stacks

Microstrip’s edge is exposed to air so its effective Dk is lower (typically 3.2–3.6 for an FR-4 core with Dk≈4.2), which means a given impedance needs a wider trace than stripline — easier to print accurately but noisier. Stripline, sandwiched between planes, is the workhorse for parallel high-speed buses (DDR, PCIe) where isolation and controlled impedance matter more than footprint.

3. The Impedance Formulas (First-Order)

For a microstrip of width w, height h above the reference plane, with thickness t and effective Dk εeff:

Z0 ≈ 87/√(εeff+1.41) · ln(5.98·h / (0.8·w + t)) (valid for w/h between 0.1 and 3)

For an edge-coupled stripline (symmetric, two planes, trace centered), the single-ended impedance is approximated by:

Z0 ≈ 60/√εr · ln(4·b / (0.67·π·(0.8·w + t))) where b = total dielectric thickness between the planes.

These closed forms get you in the right ballpark; precise values come from the field-solver or the fab’s own impedance calculator with their material-characterized data. The key sensitivities: Z0 rises with wider traces (w) and thicker dielectric (h), falls with higher Dk. A 10% error in h (typical laminate tolerance ±10%) moves Z0 by roughly the same percentage — which is why stackup control on the dielectric thickness is as important as trace-width control.

4. Differential Impedance and the Coupling Argument

For high-speed differential pairs (USB, PCIe, LVDS), the target is the differential impedance Zdiff — typically 100 Ω (or 90 Ω for DisplayPort/USB3). The differential pair’s two single-ended traces each have Z0 (odd-mode) and the coupling between them shifts the effective values:

Zdiff ≈ 2 · Z0_odd · (1 − k) where k is the coupling coefficient set by the spacing s relative to the trace height.

The practical rule: start with each trace designed for Z0_odd ≈ Zdiff/2·(1/(1−k)) — for standard 100 Ω differential with typical spacing, each trace lands around 50–60 Ω single-ended. The space between the pair (s) governs the coupling: too tight (k high) makes Zdiff drop below target and narrows the manufacturable tolerance; too wide and the pair is really two single-ended lines. A common spec is s/trace-width ratio between 2 and 3 with a uniform, continuous ground pour around the pair and no crossing splits.

5. Stackup Design — the Foundation

The impedance is a property of the cross-section, so the stackup is decided before routing. The steps:

• Pick a 4/6/8-layer stack with continuous reference planes; the reference (ground) plane directly below a signal layer must be unbroken across that signal’s route.
• Place controlled-impedance signal layers adjacent to solid planes — microstrip on L1/Ltop over L2 ground; stripline in L3 between L2/L4.
• Choose the dielectric thickness and Dk to meet the Z0 target with trace widths the fab can hold (≥ 3–4 mil print, typically).
• Add the manufacturing tolerance budget: the fab will quote a ±10% (or ±5% with tighter controls) impedance spec; your timing and noise margins must live inside it.
• For the power planes that also act as reference planes for microstrip signals, keep a solid plane under the high-speed region and stitch vias around the layer transitions.

A 50 Ω microstrip on a 0.1 mm (4 mil) core with εr 4.2 needs roughly a 180–200 µm (7–8 mil) trace; a 100 Ω differential pair on the same stack ends up around the same width with 6–8 mil spacing. The exact numbers come from the solver or the fab’s spreadsheet — never from memory at layout time.

6. Worked Example — 100 Ω Differential Pair + 50 Ω RF Trace, 6-Layer Stack

Target: route a 100 Ω differential pair (USB 2.0 high-speed) and a 50 Ω single-ended RF trace on a 6-layer board with standard FR-4 (εr ≈ 4.2 for outer microstrip, 4.4 inner), plane spacing 4 mil for outer, 8 mil for the inner stripline.

• Microstrip (L1, outer) for the RF trace: target 50 Ω. With h = 4 mil, εeff ≈ 3.5, t = 1.4 mil (1 oz), the formula gives w ≈ 8 mil; confirm with the fab solver. Verify the return path is a solid L2 ground beneath.
• Differential (L3 stripline between L2/L4): b = 8 mil total, εr = 4.4. For Zdiff = 100 Ω with s = 8 mil, the solver yields each trace ≈ 5.5–6 mil wide; then check the coupling keeps Zdiff close to 100 Ω across the fab tolerance.
• Tolerance: the fab quotes ±10% (45–55 Ω single-ended, 90–110 Ω differential); the USB spec tolerates 90–110 Ω — inside, but only if the stacking is uniform; require the fab to control the inner-layer dielectric thickness.
• Routing rules: keep the differential pair parallel, length-matched to ±5 mil, with an even number of layer changes (each via transition stitched with at least two ground vias).
• Impedance coupons: the fab will etch coupons and measure Z0/TDR on the production panel — ask for the report and verify your computed widths fall in the measured range.
• Decoupling sanity: the reference and bypass network still matter at the supply side — use the decoupling capacitor calculator to confirm the local PDN caps for the driver/receiver, because a clean power pin is part of a clean signal.
• For the EMI side of the same board, the EMI filter calculator sizes any filter at the I/O that the fast edge otherwise excites.

7. Common Mistakes

• Broken reference plane: a slot cut in the ground under a high-speed trace turns the controlled impedance into a random inductance — the single most common “impedance failure” that no width change fixes.
• Routing over a plane split (GND/PWR boundary): the return current cannot cross the split; it detours, adding inductance and coupling.
• Trusting a single-width estimate: using a formula with the wrong Dk/thickness; the fab’s material characterization is the only trustworthy basis.
• Ignoring the +/- tolerance: designing to exactly 50.000 Ω leaves no margin for the ±10% fab spread — add margin in your stackup.
• Un-even, widening differential spacing: the impedance varies along the pair where it spreads to avoid vias; keep the pair tightly coupled end to end.
• Forgetting the vias: each via adds ~0.2–0.5 nH and a stub; high-speed vias need back-drilling or short barrels.

8. FAQ

Q: Do I need impedance control on every trace? A: Only when the edge speed and trace length make reflections and ringing significant (roughly when L_trace > λ/10 or the rise time is comparable to the propagation delay). Short, low-speed traces need no control.

Q: What impedance should I pick? A: Follow the interface spec — 50 Ω single-ended for RF and most logic test, 100 Ω differential for USB/LVDS, 90 Ω for some USB3/DisplayPort; never invent a value the receiver does not expect.

Q: Why does my measured impedance differ from the formula? A: The manufactured Dk, the etch width (the fab etches wider or narrower), and the dielectric thickness all vary; this is exactly why the fab must quote their controlled-impedance process and measure coupons.

Q: Can I control impedance without a special stackup? A: Yes — on a standard 2-layer board, a microstrip over a solid ground is a controlled impedance if you get the width right and keep the plane solid; but multi-layer controlled stacks give the reproducibility and isolation the fast interfaces need.

9. Conclusion

Impedance control is not an exotic extra — it is the arithmetic of trace geometry meeting the transmission-line physics, and it lives or dies with the stackup decision and the routing discipline. Compute the widths with the right material numbers, keep the reference planes unbroken, hold the differential pairs coupled and matched, budget the fab’s ±10%, and confirm with the manufacturing coupons. Do that and the high-speed and RF traces will behave like the model, not like the mystery.