1. Introduction — EMC Is Decided in Layout, Not in the Filter BOM

Electromagnetic compatibility problems are almost always discovered at the test house, after the layout is frozen, and the standard “fix” — adding ferrite beads and capacitors until the scan passes — is expensive, unpredictable and often counterproductive. The reason is that emissions and immunity are determined by where the return currents flow, not by the schematic’s component values. A 1 cm² loop carrying 100 mA of switching current radiates more than a correctly routed current ten times larger. This guide covers the physics that links layout to emissions, the grounding strategies (single-point, multi-point, hybrid, split planes) and when each is appropriate, the design of a low-impedance ground plane with vias, the return-path discontinuity problem and its fixes, the placement of filters and decoupling, cable and connector treatment, and a practical EMC-oriented layout checklist. It complements the PCB stackup and impedance-controlled routing guides on this site.

2. The Physics: Loops, Antennas and Return Paths

A current flowing in a loop of area A radiates a field that grows with frequency and with the loop area. The maximum far-field electric field from a small loop (in free space, worst case) is approximately:

E (µV/m at 3 m) = 1.316e-14 · f² · A · I / r

with f in Hz, A in cm², I in A and r in m. The practical reading of that formula: emissions scale with f² (so the highest-frequency edges dominate), scale linearly with the loop area, and scale with the current amplitude. Reducing the loop area is therefore the single most powerful EMC action available in layout — and the loop area is defined by the signal trace and its return path. At DC the return takes the lowest-resistance path; at high frequency it takes the lowest-inductance path, which means it flows directly beneath the signal trace in the reference plane (this is the image-current effect). Any discontinuity in that reference — a plane split, a slot, a via switching reference layers, a connector pinout that breaks the plane — forces the return current to detour around it, enlarging the loop and creating both emissions and a signal-integrity problem. This is the origin of the two most important layout rules: (1) keep a solid, unbroken reference plane under every signal, and (2) never route a fast signal across a plane split.

3. Grounding Strategy

Strategy	Structure	Appropriate for	Risks
Single-point (star)	All grounds meet at one node	Low-frequency, precision analog, mixed-signal with one converter	High inductance; inadequate above ~1 MHz
Multi-point	Low-impedance plane used everywhere	Digital, high-frequency, RF	Common-impedance coupling if return currents share paths
Hybrid / partitioned	One plane, partitioned layout zones	Mixed analog/digital boards	Partition must follow current, not the schematic
Split planes joined at one point	Separate analog/digital planes, single bridge	Boards with a single mixed-signal converter	Any signal crossing the split creates a large loop

The current best practice for mixed-signal boards is not to split the ground plane at all but to partition the layout: keep the analog components and their return currents in one region, the digital in another, and place the ADC so that its analog and digital return pins are the boundary. The converter’s ground pins are the bridge; the plane stays continuous so that no return current has to detour, and the low-frequency analog return currents (which follow the path of least resistance, not least inductance) naturally stay in the analog region because the components and traces are there. Splitting the plane seems tidier but creates the plane-split crossing problem for every signal that must cross — which is usually every signal going to the converter. If a split is unavoidable, all signals crossing it must be routed over a stitching capacitor or a bridge, and the bridge must be wide and short.

4. Designing the Ground Plane

A ground plane is not a component you place; it is a structure whose impedance must be low at the frequencies of interest. Key points: (a) copper thickness and width set the DC/low-frequency impedance; at high frequency the impedance is dominated by inductance, so a wide plane and short return paths matter more than extra copper thickness; (b) vias stitching the top and bottom ground pours around the board perimeter and along board edges reduce the plane’s resonant behaviour and the “plane antenna” effect — place them every 5–10 mm, or λ/20 at the highest frequency of interest (λ/20 at 500 MHz in FR-4 ≈ 15 mm); (c) ground vias next to every signal via that changes layers, so the return current has a nearby path between planes; (d) avoid slots and cut-outs under fast signals and under connectors; (e) keep the ground plane continuous under the crystal, the switching regulator and any high-current loop. The stitching-via density is a direct trade against emissions: a plane with sparse stitching radiates at its resonant frequencies, and the resonance bands are exactly where the EMC scan will fail.

5. Decoupling, Filtering and the Power Distribution Network

Decoupling capacitors do not “supply current” — they hold the power distribution network’s impedance low across frequency so that the IC’s switching current is drawn locally instead of circulating through the board’s power loop. Practical design: one small (100 nF) capacitor per power pin, placed with the shortest possible loop (via-in-pad or via immediately adjacent to the pad); a bulk capacitor per rail and per region to cover the low-frequency band; and, for high-speed devices, the plane capacitance and the capacitor’s own mounting inductance dominate. The mounting inductance (~1 nH for a well-placed 0402) sets the capacitor’s high-frequency limit: above self-resonance the capacitor is an inductor, so multiple smaller capacitors of different values placed in parallel are far more effective than one large one. The required capacitance and impedance target are computed from the allowed ripple and the current transient with the decoupling capacitor calculator — set the target impedance from the load’s transient current and the allowed voltage deviation, then verify that the parallel network stays below it across the band. For conducted emissions and for filtering a noisy rail or a cable interface, the attenuation and corner frequency of the filter follow standard LC relations and can be checked with the EMI filter calculator; remember that an LC filter’s attenuation at high frequency is limited by the capacitor’s ESL and the inductor’s parallel capacitance, so the layout of the filter itself must keep its loop tiny.

6. Cables, Connectors and I/O

Cables are the most efficient unintentional antennas on the board, so I/O treatment decides much of the radiated emissions result. Rules: (a) filter or terminate every cable signal at the connector, at the connector, not 2 cm inside the board — the un-filtered stub between the connector and the filter radiates; (b) provide a low-impedance ground return for each cable, and connect the cable shield to the chassis/ground plane through a low-inductance path (a 360° bond is ideal; a pigtail is a 50 nH inductor and mostly useless at high frequency); (c) common-mode chokes on differential or power cables suppress the common-mode current that cables radiate, but the choke must be placed so that the return current path stays controlled; (d) never route a clock or a switching node to a connector without filtering; (e) for the power input, place the filter with the smallest possible loop between the input capacitor, the filter and the ground plane. A useful diagnostic: measure the common-mode current on the cable with a current probe. If the emissions track the cable current, the problem is the I/O treatment; if they track the board’s near field, the problem is the layout loop.

7. Worked Example — 24 V to 5 V Buck with a 2 MHz Switching Node

Target: a 24 V→5 V, 3 A buck at 2 MHz in a plastic enclosure, needing CISPR 32 Class B radiated emissions.

• Identify the dominant loop: the input capacitor → high-side switch → ground loop. The switching current is a 3 A trapezoid with ~10 ns edges; the loop area must be minimized. Place the input capacitor directly across the switch and the diode/synchronous FET, on the same copper layer, with the smallest possible enclosed area.
• Ground strategy: one continuous ground plane; the power stage’s return current flows in the plane directly under the switch node, so no analog or clock signal may be routed in that region or across any slot in the plane.
• Switching node treatment: keep the switch node copper as small as possible (it is the highest-dv/dt node and the main capacitive coupling source), and never route anything underneath it on adjacent layers — the switch node’s copper couples via the inter-plane capacitance.
• Stitching: place ground vias every 5 mm around the power-stage perimeter and adjacent to every layer-changing signal, especially the switch node and the feedback trace.
• Filtering: an input LC filter (1 µH + 10 µF) attenuates the 2 MHz ripple; the EMI filter calculator is used to set the corner (say 200 kHz) and to confirm the attenuation (>20 dB at 2 MHz) with the real capacitor ESR/ESL. The filter’s loop must be as tight as the power stage’s.
• Feedback trace: route the 5 V feedback away from the switch node and the inductor, over the ground plane, with a small series resistor and a parallel capacitor placed at the controller; this trace is a high-impedance node and a classic coupling victim.
• Verification: near-field probe scan before the chamber to locate the hot spots, then a pre-compliance scan; expect the residual failure to be the cable’s common-mode current if the enclosure is plastic and the output cable leaves unfiltered.

8. Estimating Radiated and Conducted Emissions Before You Build

Layout decisions can be checked numerically before the board is made, and doing so focuses the effort on the loops that actually dominate. The starting point is the maximum emission from a current loop, which for a small loop (circumference much less than a wavelength) is approximately:

E(dBµV/m) ≈ 20·log10( 263 × 10⁻¹⁶ × f² × A × I / r ) (f in Hz, A in m², I in A, r in m, far field)

The practical reading of this expression is that the radiated field is proportional to the loop area A, to the current I, and to the square of the frequency f. Reducing the loop area by a factor of 10 is a 20 dB improvement — dramatically easier than filtering or shielding, and free at layout time. This is why the switching converter’s input and output loops, the gate-drive loops and the return paths of high-speed signals deserve attention before any filter is chosen. The second calculation worth doing is the “critical frequency” or λ/2 resonance: a trace or a cable becomes an efficient radiator when its length approaches a quarter or a half wavelength, so a 0.3 m cable resonates near 250 MHz (half wavelength in free space) and radiates strongly at its harmonics. Cable length, therefore, is a design variable in EMC, not a packaging afterthought. A short script that evaluates these two relationships over the design’s frequency range identifies which loops and which cables must be addressed first:

import math

def loop_field_dBuVm(freq_hz, area_m2, current_a, distance_m):
    """Maximum far-field E from a small current loop (worst-case orientation)."""
    e = (263e-16 * freq_hz**2 * area_m2 * current_a) / distance_m
    return 20.0 * math.log10(max(e, 1e-30) / 1e-6)   # V/m -> dBuV/m

def half_wave_resonance(length_m):
    """Frequency at which a conductor of this length is a half-wave radiator."""
    return 3e8 / (2.0 * length_m)

# Example: 2 MHz buck converter, 12 V/2 A, 25 mm^2 input loop,
# measurement at 3 m.
for f in (2e6, 10e6, 30e6, 100e6, 300e6):
    print(f"{f/1e6:8.1f} MHz  loop  E = {loop_field_dBuVm(f, 25e-6, 2.0, 3.0):7.1f} dBuV/m")

# Cable resonance: which of our harness lengths ring inside the test band?
for L in (0.10, 0.30, 1.00):
    print(f"cable {L*100:5.1f} cm  half-wave at {half_wave_resonance(L)/1e6:7.1f} MHz")

Three conclusions typically fall out of this exercise. The loop’s contribution rises steeply with frequency, so above 100 MHz the parasitic loops (decoupling vias, connector pin pairs, cable-to-chassis paths) usually dominate over the switching loop. Cables of harness length are the largest antennas on the product and must be protected at the connector. And the highest-frequency content comes from the fastest edges, so controlling the edge rate — with a gate resistor, a ferrite bead or a slower driver — reduces the emission spectrum above the edge’s knee frequency even though it does nothing at the fundamental.

9. Interface Protection, Filtering and the Cable as an Antenna

Once the board’s internal loops are addressed, the product’s remaining emissions come out through its cables, and the remaining immunity failures enter the same way. The connector is therefore the most important EMC component on the board, and the measures at that boundary are worth a section of their own.

• Ground the connector’s return to the chassis/plane at the connector: a connector with a long, thin return path forces the cable’s common-mode current to flow through the board’s ground, where it couples into everything. A low-inductance return (multiple pins, a wide strap, a grounded shell) gives the current a local path.
• Filter at the connector, not inside the board: a filter placed a few centimetres inside the board leaves an unfiltered trace acting as an antenna inside the enclosure. Place the series element and the shunt capacitor with the shortest possible path to the connector’s ground reference.
• Common-mode chokes for differential interfaces: twisted-pair and differential links radiate mainly common-mode current; a common-mode choke with a high impedance in the band of interest (and a low differential impedance so the signal is unaffected) is the standard remedy.
• Protection devices placed after the filter, referenced to the connector ground: TVS diodes on a long cable see the surge; their return path must not cross the board’s audio/analogue reference.
• Shield termination: a cable shield grounded at one end only is a low-frequency strategy; at RF the shield is usually grounded at both ends (or through a capacitor) to form a current path around the enclosure’s perimeter, at the cost of the shield’s own current flow — a decision that depends on whether the dominant problem is ground-loop noise (low frequency) or radiated coupling (high frequency).
• The chassis is part of the circuit: a metal enclosure with poor bonding between its panels is a slot antenna; the bond’s inductance at the frequencies of interest, not the DC continuity, determines the shielding effectiveness.

Pre-compliance testing is the practical way to confirm these choices: a near-field probe (a magnetic loop) swept over the board while monitoring a spectrum analyser locates the radiating loops quickly; a simple current probe on each cable identifies which cable carries the common-mode current; and a conducted-emissions measurement in a controlled setup (or the actual test house) verifies the mains port. Debugging rules that save the most time: change one thing at a time; find the source with a near-field probe before filtering (a filter applied to the wrong cable gives no result); remember that a ferrite added temporarily at a connector will often “fix” the symptom while leaving the real coupling path in place; and always re-measure after the enclosure is closed, because the enclosure changes both the coupling and the resonances.

10. Common Mistakes

• Splitting the ground plane and then crossing the split with signals: creates the large loop that radiates; if a split exists, no fast signal may cross it without a stitching path.
• Ignoring the return current when placing a filter: a perfectly designed filter with a 2 cm return stub has no high-frequency attenuation at all.
• Switching node copper left large “for thermal reasons”: it becomes the dominant capacitive coupling source; minimize the node and use other copper for heat.
• Decoupling capacitor with a long via loop: the mounting inductance dominates and the capacitor is ineffective above a few MHz.
• Shield connected with a long pigtail: the pigtail’s inductance destroys the shield’s high-frequency effectiveness; bond the shield to the plane all around.
• Chasing the scan with ferrites at the end: an uncontrolled patch that may shift the emissions to another band; fix the loop area instead.

11. FAQ

Q: Should I use a split ground plane for mixed-signal? A: Usually no. Partition the layout and keep the plane continuous; the converter’s ground pins are the bridge. Splitting only helps in specific cases and creates the plane-crossing problem.

Q: How many stitching vias do I need? A: Every 5–10 mm around the perimeter and along high-speed routes, plus one adjacent to every layer-changing signal via; denser is better and costs nothing but space.

Q: Do ferrite beads really help? A: They help when they are placed at the right point (right at the connector, with a low-inductance return) and when the emissions are cable-driven; used as an afterthought on an unfiltered board they often just move the problem.

Q: How do I decide between a 2-layer and a 4-layer board when the budget is tight? A: Compare the cost of the extra layers with the cost of the alternatives (a shield, a filter, a redesign after a failed scan). Emitted-field scaling goes as the loop area, and a reference plane adjacent to the signal layer typically reduces the dominant loop by an order of magnitude — a 20 dB advantage for a fraction of the product cost. The honest framing is that the 4-layer board is not a luxury but the cheapest EMC measure available.

Q: What is the single most common cause of a first-pass EMC failure? A: In the author’s experience, an unfiltered cable leaving the enclosure — the product’s largest antenna — followed closely by a switching-node or a decoupling loop that was laid out with the current return path ignored. Both are layout decisions rather than component choices, which is why the layout review is where EMC is actually designed.

Q: How do I verify EMC before the certification lab? A: Use a near-field probe to find the hot loops, a current probe to identify which cable carries the common-mode current, and a pre-compliance scan in a local setup to confirm the margin; a 6 dB margin measured pre-compliance is a reasonable target, since the enclosure and the final cable routing will change the result.

12. Conclusion

EMC is the physics of current loops, and layout is where the loops are defined. Keep the reference plane continuous, minimize the area of every high-di/dt loop (power stage, filters, decoupling), control the return path of every fast signal and every cable, treat the I/O at the connector, and stitch the ground structure so it behaves as a plane rather than an antenna. Do it in layout and the EMC test becomes a verification instead of a redesign.