1. Introduction — The ADC Is Only as Good as Its Front End

A modern high-resolution ADC (12–24 bits, up to 10 MSPS SAR or thousands of samples-per-second delta-sigma) digitizes a signal that must already be band-limited, level-matched, low-impedance and clean. The front-end driver amplifier and its RC network are what transform the raw sensor signal into the exact waveform the ADC’s sampling circuit can capture without error. Get it wrong and the converter’s datasheet ENOB (effective number of bits) never materializes: the driver’s settling time corrupts the sample, the anti-alias filter’s corner alias-shifts noise into the band, the kickback from the sample switch rings into the reference, or the reference noise dominates everything. This guide covers the amplifier selection and drive requirements, the anti-alias filter design, the RC charge-bucket (Kenetic/R-C) network that isolates the ADC input, settling-time math, the reference and its bypass, noise budgeting, and a complete worked example for a 16-bit SAR acquisition chain. It complements the instrumentation amplifier and precision reference guides on this site.

2. What the ADC Front End Must Do

The input stage of a SAR ADC is a switched-capacitor sampler: during the sampling phase, a tracking switch connects the internal sampling capacitor (Cs, often 4–40 pF with a series Rsw of 100–500 Ω) to the input pin, drawing a transient charge from the external network. The front-end network must:

• Present a low enough source impedance that the sampling capacitor charges to the input voltage within the acquisition time (a “source too slow” error — the classic missing-code / offset error on high-speed SARs).
• Band-limit the signal so that out-of-band noise (the ADC’s own thermal noise, amplifier noise, and any switching noise) does not alias into the passband.
• Drive the DC level into the ADC’s input range (often unipolar 0–Vref or bipolar ±Vref/2) — the driver op-amp sets the offset and the swing.
• Absorb the sampling kickback without degrading settling: this is the purpose of the series resistor + small capacitor (the charge-bucket RC).

A delta-sigma ADC, by contrast, samples continuously and re-quantizes; its front end is dominated by the un-decimated modulator noise and benefits from a simpler RC rather than a precision drive. Understanding which ADC you have sets the whole design.

3. The Driver Amplifier — Gain, Settling and Noise

Choose the driver amplifier by four numbers: the gain-bandwidth (enough closed-loop bandwidth to settle to the ADC’s resolution within the acquisition window), the settling time to 0.5 LSB at the ADC’s resolution, the output drive (the amplifier must deliver the transient current into the RC network without disturbing its own loop), and the noise density (the amplifier’s voltage noise, referenced to the ADC’s full-scale, should be well below the converter’s quantization noise floor).

Parameter	Typical target (16-bit SAR)	Why
Amplifier noise (RTI)	< 5 µVrms over the filter BW	Must not dominate the 1-LSB budget
Settling to 0.5 LSB	< acquisition time (e.g. 400 ns)	A slow amp leaves an error at the sample
Output impedance at f_sample	< a few Ω	Stable into the RC network
Open-loop gain at DC	> 100 dB	Low DC/offset gain error

A rule of thumb for the settling requirement: a single-pole-amplifier’s time constant τ must satisfy t_acq ≥ 8–10 τ for 0.01% (≈ 12 bits) settling; for 16 bits you need t_acq ≥ ~11–12 τ. The bandwidth needed is therefore roughly f_BW ≥ (bits-dependent factor) / t_acq.

4. The RC Charge-Bucket (Anti-Alias) Network

Between the amplifier output and the ADC input sits a series resistor Rs and a shunt capacitor Cfilt forming a low-pass filter. The resistor limits the charging current into the sampling capacitor (isolating the amplifier from the kickback), and the capacitor provides the charge reservoir for the fast sampling pulse. Two constraints fight:

• Charge-bucket adequacy: Cfilt must hold enough charge that the kickback (charge Q = Cs × V) collapses only a small voltage; a common rule is Cfilt ≥ 20 × the ADC input capacitance, so the tracking switch’s disturbance stays below an LSB. 1–2 nF is typical for SARs.
• Settling time: Rs and Cfilt form a time constant τ = Rs × Cfilt that must settle to 0.5 LSB within the acquisition time — otherwise the sample is taken before the filter output has reached the true value.

The amplifier’s own output impedance plus Rs must be low enough against Cfilt that the network does not become a second, slower pole that the loop cannot control. The resistor divider also attenuates: with an ideal ADC the source current is tiny, but at high sample rates Rs×Cs×f_s can become non-negligible; keep Rs small enough that the DC error stays under an LSB. The resistor value itself also adds to the source impedance seen by the sampler, setting the effective time constant of the interaction.

5. Anti-Alias Filter Design

For a sampled system, any signal (or noise) above Nyquist (f_s/2) folds into the band. The anti-alias filter must attenuate out-of-band content to below one LSB-equivalent at the ADC input. A first-order RC (the Rs×Cfilt above) rolls off at only 20 dB/decade — often insufficient for broadband noise; a second-order active stage (Sallen-Key) or a higher-order passive network is needed when the amplifier noise extends far up. The corner frequency is chosen well above the signal band but below Nyquist: a typical rule is f_corner ≈ 0.05–0.3 × f_s, and the required order comes from how much attenuation at f_s/2 the noise budget demands: attenuation_dB = 20·n·log10(f_s/2 / f_corner). The Sallen-Key filter calculator turns the target corner, Q and gain into component values for the active stage directly.

Because the RC network also does the anti-alias job, many designs merge the two: a low second-order “charge bucket + series R” passive filter, then rely on the ADC’s internal decimation or the noise shaping for the rest. The math is the same — only the required attenuation per application differs.

6. Reference and Its Noise

The ADC’s reference (Vref) sets the full-scale; its noise appears directly on every code. A 16-bit system with Vref = 4.096 V has an LSB of ~62.5 µV, and the quantization noise is ~18 µVrms; the reference noise must stay a fraction of that to keep ENOB near the datasheet value. Use a clean, buffered reference (a precision bandgap or a dedicated ADC reference), decouple it with a large ceramic + a bulk capacitor at the REF pin, and keep the REF return short and separate from the digital return. The sample-and-hold kickback also couples into the reference during acquisition; a suitable decoupling capacitor must hold the voltage stable for the acquisition window.

7. Worked Example — 16-bit, 1 MSPS SAR ADC Front End

Target: digitize a ±5 V industrial sensor through a ±5 V to 0–5 V level shift, sampled at 1 MSPS by a 16-bit SAR with t_acq = 500 ns, Vref = 4.096 V, input capacitance Cs = 15 pF, Rsw = 300 Ω.

• Resolution budget: LSB = 4.096 V / 65536 ≈ 62.5 µV; 0.5 LSB settling target ≈ 31 µV.
• Charge bucket: Cfilt = 2.2 nF (≈ 150 × Cs) absorbs the kickback: ΔV = Q/C = 15 pF × 4.096 V / 2.2 nF ≈ 28 µV — below 0.5 LSB. Good.
• Settling: with Rs_series = 50 Ω and source impedance of the amplifier ~few Ω, τ = 50 × 2.2 nF = 110 ns; t_acq / τ = 500/110 ≈ 4.5 τ — not enough for 16 bits. Reduce format: choose Rs = 20 Ω and Cfilt = 1.5 nF → τ = 30 ns, t_acq/τ ≈ 16 τ → settles to < 0.5 LSB. The smaller Cfilt still ≥ 100×Cs, acceptable.
• Amplifier: DC-coupled driver with GBW so the closed loop settles in < 300 ns; pick an amp with voltage noise < 3 nV/√Hz so that over the filter BW (say 30 kHz) the noise ≈ 3 × √(30 kHz×1.57) ≈ 0.65 µVrms — far below the 18 µVrms quantization floor.
• Reference: a 4.096 V precision reference, REF decoupled with 10 µF ceramic + 1 µF; keep the return separate.
• Level shift: the ±5 V to 0–5 V stage (or an in-amp) with gain 0.5 and offset +2.5 V; the Ohm’s-law calculator and a divider check the resistor ladder values if you choose a passive level shift, and the parallel resistor calculator sizes the divider Thevenin resistance against the ADC source requirement.
• Verify on the bench: a 1 kHz sine at −1 dBFS should produce an SNR within ~2 dB of the datasheet; if the low-order harmonics or a broad noise floor appear, the front-end (settling or filter) is the cause.

8. Common Mistakes

• Source impedance too high: the sampling capacitor cannot fill in time — the classic “1 LSB offset that vanishes with a better buffer”.
• Too large a series resistor: the RC time constant extends past the acquisition window; the ADC “settles” only on paper.
• Under-sized charge bucket: a tiny Cfilt lets the kickback collapse the input voltage, producing a code ripple at the sample rate.
• No anti-alias before a fast sampler: broadband noise aliases and permanently caps ENOB regardless of ADC quality.
• Shared, noisy reference return: reference noise rides on every code; separate the return path.
• Ignoring the amplifier settling at the top of the range: a slow op-amp makes the largest codes lag — the error shows at the extremes of the input range.

9. FAQ

Q: Why is a big capacitor after the op-amp so important? A: It provides the instantaneous charge for the sampling switch (the “bucket”); without it the op-amp has to source the current (and settle), or the input voltage dips during acquisition.

Q: Can I just use a tiny RC and rely on the ADC filter? A: In SAR ADCs the internal trace has limited filtering; the external RC is what stops aliasing and sets settling. In delta-sigma ADCs the modulator tolerance is higher, so a simpler network often suffices.

Q: How good must the reference be? A: Its noise should be ≤ ~1/3 of the quantization noise, and its impedance must be low at the sample frequency to ride out the kickback; modern ADCs specify a recommended REF capacitor.

Q: Why does my ENOB improve when I lower the sample rate? A: The acquisition window grows, so settling errors and kickback-injected residual charge decay further below an LSB — the front-end was the bottleneck, not the converter.

10. Conclusion

The ADC front end is a miniature system: the driver amplifier sets bandwidth and settles, the RC charge-bucket isolates and filters, the reference sets the full-scale and its noise, and the layout keeps the returns clean. Compute the settling and the kickback first (they decide Rs and Cfilt), choose the amplifier by noise and settling, then verify with a sine-wave SNR test. The front end is where 16 bits are won or lost — the converter itself rarely surprises, the network in front of it always does.