STM32G0 IWDG Nominal Timeout

Method and limits

STM32G0 training, IWDG settings: timeout = (RL+1) × divider / fLSI. Divider is 4, 8, 16, 32, 64, 128 or 256; RL is 0..4095. Enter the actual LSI frequency in Hz. Nominal counter duration only; oscillator tolerance, synchronization latency and window refresh limits are excluded. This is not a guaranteed reset deadline or a calculation for other MCU watchdogs.

Manufacturer method reference

Inputs

Use the stated units. Invalid values clear all results. Warnings identify unresolved limitations. Calculations run locally in your browser.