ADC Anti-Aliasing Filter Calculator

This tool calculates component values (R and C) for passive RC low-pass filters—single-pole or multi-pole—designed to attenuate frequencies above the Nyquist frequency (fs/2) by a specified amount. It ensures aliasing distortion is suppressed below acceptable levels before analog-to-digital conversion.

Without it, frequencies above half the sampling rate (Nyquist frequency) fold back into the baseband during sampling, corrupting the digital representation with non-recoverable artifacts. The filter enforces bandlimiting to preserve signal fidelity and meet Shannon-Nyquist reconstruction requirements.

“Max Signal Freq” defines the highest frequency component you intend to preserve in your analog signal. “Attenuation @ Nyquist” specifies how much suppression (in dB) is required at fs/2 — typically ≥40–80 dB — to ensure aliased energy falls below the ADC’s noise floor or LSB threshold.

A 1st-order (single-pole) RC filter provides −20 dB/decade roll-off; higher orders (e.g., 2nd–4th) yield steeper attenuation but require more components and introduce phase shift and stability considerations. Use order = 2 for balanced performance in most general-purpose data acquisition systems.

Common sample rates range from 1 kSPS (sensor monitoring) to 10 MSPS (audio/video), while max signal frequencies span DC–100 kHz for industrial sensors or up to several MHz for RF sampling. Always ensure fsig < fs/2 — the calculator flags invalid inputs where this is violated.

No — this tool computes only passive RC ladder networks (e.g., cascaded 1st-order stages). For optimized active filters with precise response shaping (Butterworth, Bessel, etc.), use dedicated filter design software or op-amp-based design tools; this calculator serves as a quick first-pass approximation.

Check that “Attenuation @ Nyquist” is set high enough (≥60 dB is common for 12+ bit ADCs) and that “Filter Order” matches your physical implementation. Also verify “Max Signal Freq” isn’t too close to fs/2 — ideally keep fsig ≤ 0.4×fs to allow transition-band margin.

Choose standard E12/E24 resistor and capacitor values nearest to the computed results. Prioritize tight-tolerance (1% or better) components for consistent cutoff behavior. Account for parasitic capacitance (e.g., PCB traces, ADC input capacitance) — especially critical above ~100 kHz — and re-simulate if precision is paramount.

No — it assumes ideal source and load conditions. In practice, ensure the filter’s output impedance (especially R) is significantly lower than the ADC’s input impedance (typically ≥10×) to avoid loading errors and settling-time degradation. Buffering may be needed for high-R designs.

The calculator derives fc based on fsig, fs, and required stopband attenuation — not a fixed multiple of fsig. It places the effective cutoff to meet the specified attenuation at fs/2 while preserving gain flatness up to fsig, often resulting in fc ≈ 1.1–1.5×fsig depending on order and attenuation target.