STM32 ADC Sampling Time Calculator

This tool calculates three key timing parameters: total sampling time (including acquisition and hold phases), full conversion time per channel, and the maximum achievable sampling rate (Hz) for a given ADC configuration. It accounts for ADC clock frequency, resolution, sampling cycles, source impedance, and multi-channel sequencing.

Insufficient sampling time causes incomplete capacitor charging in the ADC’s input sample-and-hold circuit, leading to gain error and reduced effective resolution—especially with higher source impedances. This calculator ensures the selected sampling cycles meet the minimum required for your signal source and desired accuracy.

“Sampling Cycles” refers to the number of ADC clock cycles allocated to charge the internal sampling capacitor (e.g., 1.5, 7.5, 13.5, or 28.5 cycles on most STM32 series). “ADC Clock” is the frequency of the clock driving the ADC peripheral (typically derived from APB2 or dedicated ADC prescaler), not the system core clock.

Higher source impedance slows charging of the ADC’s internal sampling capacitor (typically ~10 pF). The calculator uses the RC time constant model (T_acq ≈ 1.5 × R_S × C_sample) to recommend minimum sampling cycles—e.g., 10 kΩ typically requires ≥13.5 cycles at 30 MHz ADC clock for 12-bit accuracy.

Valid values depend on the STM32 series but commonly include 1.5, 7.5, 13.5, 28.5, 41.5, 55.5, 71.5, and 239.5 ADC clock cycles. These correspond to register settings (SMP[2:0]) and must be selected to satisfy T_sample ≥ 1.5 × R_S × C_sample + t_STAB (stabilization time).

In sequence mode (e.g., regular or injected channels), total conversion time scales linearly with channel count: T_total = N_ch × (T_sampling + T_conversion). The calculator automatically computes the effective system sampling rate (1 / T_total) for continuous conversions across all channels.

“Single” mode performs one conversion per trigger; “Continuous” repeats conversions indefinitely; “Scan” sequences multiple channels. The calculator assumes Scan/Continuous for multi-channel throughput calculations. For single-shot applications, ignore channel count scaling in max rate output.

Common causes include excessive source impedance requiring long sampling times, high resolution increasing conversion cycles (e.g., 12-bit needs more cycles than 10-bit), or misconfigured ADC clock (e.g., using system clock instead of prescaled ADC clock). Verify your ADC clock is correctly derived from APB2/PCLK2 and within datasheet limits (e.g., ≤36 MHz for most STM32H7, ≤14 MHz for older F1/F3).

Yes—by computing the true maximum sampling rate, you can determine if it satisfies the Nyquist–Shannon criterion for your signal bandwidth. For example, to capture a 10 kHz sine wave without aliasing, ensure the calculated max rate ≥ 20 kHz (preferably ≥ 5× for practical anti-aliasing filter design).

Higher resolution increases the number of ADC clock cycles needed for conversion (e.g., 12-bit ≈ 12.5 cycles, 16-bit ≈ 16.5 cycles on most SAR ADCs). This directly lengthens total conversion time and reduces maximum sampling rate—especially critical in high-speed or multi-channel applications.