1. Introduction — The Feedback Signal That Decides the Loop

Every advanced motor control scheme — field-oriented control, sensorless estimation, torque limiting, stall detection, overcurrent protection — depends on one signal: the phase current. The quality of that signal sets the ceiling on everything the control loop can achieve. A current sense with 10% gain error and 50 µs of effective delay will produce a torque ripple, a mis-estimated rotor angle and a protection threshold that either trips on inrush or fails to protect the bridge. Yet current sensing is often the last part of the design to be reviewed and the first to be compromised for cost. This guide covers the sensing methods (ground-referenced shunt, inline shunt with a current-sense amplifier, Hall effect, fluxgate and the DC-link single-shunt technique), the signal-conditioning design that follows the shunt (amplifier selection, gain, offset, bandwidth and the layout that makes the measurement real), the timing relationship between the PWM, the current sampling instant and the ADC, the reconstruction of three phase currents from a single DC-link measurement, and a complete worked example for a 48 V, 20 A field-oriented control design. It complements the motor control and brushless commutation guides on this site.

2. Choosing a Sensing Method

Method	Accuracy / bandwidth	Isolation	Cost	Typical use
Low-side shunt (below the bridge)	Good, but only when the low-side switch is on	None (ground-referenced)	Lowest	Overcurrent protection, simple control
Inline (phase) shunt with CSA	Best accuracy and bandwidth	None (needs high common mode)	Medium	FOC servo drives
Single DC-link shunt	Good with careful timing	None	Lowest per phase	Cost-sensitive FOC (fans, pumps)
Hall effect (open/closed loop)	Medium accuracy, DC-capable	Yes (magnetic)	Medium-high	High current, galvanic isolation, EV traction
Fluxgate / current transformer	High accuracy; CT cannot measure DC	Yes	High	Instrumentation, high-power drives

The decisive constraints are the common-mode voltage the amplifier must survive and the moment in the PWM cycle when the current is valid. A low-side shunt sits at ground potential (easy to amplify) but carries current only during the low-side conduction interval, so in a three-phase inverter with continuous modulation it can be sampled only in specific windows — and at high modulation index or high duty those windows vanish. An inline shunt in the phase leg sees the full PWM common-mode swing (tens of volts moving at 10–50 V/ns) and requires a current-sense amplifier with a high common-mode input range and good common-mode rejection at that edge rate, but it can be sampled at any time the switching noise has settled. The single DC-link shunt is the cheapest way to get all three phase currents, at the cost of a reconstruction algorithm that depends on the switching state, as detailed in section 6. A useful first-order design check of the sense resistor’s dissipation and the resulting voltage developed at rated current is a straightforward application of Ohm’s law, which the Ohm’s law calculator handles directly, and the mechanical and control envelope of the drive is bounded by the load’s torque-speed requirement, which is where the motor control calculator comes in.

3. Shunt Selection and the Sense Chain

The shunt is a trade: more resistance gives more signal and better signal-to-noise, but more loss and more self-heating. Start from the maximum current and the acceptable dissipation:

P_shunt = I_rms² · R_shunt < (0.5–1%) of rated power; V_sense = I_max · R_shunt

A 1 mΩ shunt at 20 A dissipates 0.4 W and develops 20 mV — a signal that demands a low-offset amplifier. A 5 mΩ shunt dissipates 2 W and develops 100 mV — easier to amplify but a 2 W heater inside a sealed drive. The practical sweet spot for small drives puts V_sense at 50–100 mV at rated current, which for a 20 A drive means 2.5–5 mΩ. Key parameters of the shunt itself: a low temperature coefficient (50 ppm/°C or better; at 100 ppm/°C and a 100 °C rise the resistance drifts 1%, directly a 1% gain error), a four-terminal (Kelvin) construction so the sense connections do not include the solder-joint resistance, and a power rating with margin for the ambient inside the enclosure. Inductance matters at high di/dt: a wirewound shunt can add tens of nanohenries, which rings with the amplifier input capacitance and corrupts the fast current edge; low-inductance metal-element or foil shunts are preferred for switching currents.

The amplifier chain: a difference amplifier or a current-sense amplifier with an input offset in the tens of microvolts, a gain that scales V_sense to the ADC’s range (e.g. 20 mV × 50 = 1 V for a 3.3 V ADC with a 1.65 V reference offset), a bandwidth of at least 10× the control loop’s bandwidth (and enough to reproduce the current ripple for protection), and a common-mode input range covering the full bus voltage plus the switching overshoot. Offset is the dominant error at low current: a 100 µV offset on a 20 mV full-scale signal is 0.5% of full scale but 50% of a 10% current reading, which is why torque accuracy at low load is a current-sense problem. Auto-zero or chopper amplifiers eliminate offset drift at the cost of some switching artefacts at the chopping frequency; be careful that the chopping frequency does not alias with the PWM or the ADC sampling.

4. Layout and Noise — Where Measurements Actually Fail

The sense chain’s error budget is usually dominated by noise and layout, not by the amplifier’s datasheet:

• Kelvin sense connections: route the two sense traces from the inside of the shunt’s terminals, as a tightly coupled differential pair, away from the power current path. A single-ended trace that shares any part of the high-current path adds an IR drop that varies with load.
• Common-mode transients: in an inline shunt the common-mode node slews with the phase voltage at every switching edge. The amplifier’s common-mode rejection at high frequency, not at DC, is the relevant specification; add a small differential RC filter (with matched resistors and a capacitor to ground on each input) close to the amplifier to attenuate the edge, and check that the filter’s corner does not slow the signal below the protection bandwidth.
• Grounding: the amplifier’s reference and the ADC’s reference must be the same quiet node; taking the amplifier’s ground return through the power ground injects the bridge’s switching currents into the measurement.
• Keep-out and shielding: do not route the sense pair under the power stage or parallel to the phase node; use a ground plane reference and keep the loop area minimal.
• ADC side: the sampling capacitor draws a charge pulse at every conversion; the driver must settle within the ADC’s acquisition time. Place the RC filter after the amplifier with a time constant compatible with the required sampling rate, and verify the settling with the ADC’s own timing specification rather than assuming it.
• Digital and PWM noise: gate-drive currents return through the power ground; if the analogue ground is not separated and single-point joined, the gate currents appear as an offset that changes with duty cycle.

5. Sampling Timing — The Most Underestimated Detail

In PWM-driven inverters the phase current is not constant: it has the fundamental component plus the ripple caused by the switching. The current that the control loop needs is the fundamental (or more precisely, the average over the PWM period), and the sampling instant must therefore be chosen so that the measured value equals that average. The standard technique is centre-aligned (symmetric) PWM with the sampling at the counter’s peak or trough:

sample at the PWM centre → measured value ≈ average current (ripple averages out symmetrically)

With edge-aligned PWM the ripple’s average is offset from the sampled value unless the sample is taken at the mid-point of the on-time, which requires the sample instant to track the duty cycle. Additional requirements: the ADC conversion must finish before the next switching event changes the current (so the sample-and-hold must occur at the right instant even if the conversion takes longer), the current-sense amplifier must have settled from the previous commutation edge (the ringing after a switching transition can last 0.5–2 µs, so the sample must be delayed by a blanking interval), and in a low-side shunt scheme the sample must fall inside the window when that phase’s low-side device is on. The relationship between the PWM frequency, the ADC sampling rate and the control-loop update rate is the same one a designer analyses when setting the timer’s configuration; the STM32 timer and ADC trigger design is covered in the timer/PWM article on this site, and the switching frequency itself is chosen via the trade between ripple, loss and control bandwidth (see the switching frequency article). The minimum-pulse-width problem is the practical limit of low-side sensing: as the duty approaches 100% or 0%, the window in which the low-side device conducts shrinks below the ADC’s minimum sampling time, and the measurement fails — the classic symptom is a drive that regulates perfectly at mid-load and loses control near full speed.

6. Single-Shunt Reconstruction

With one shunt in the DC link and a six-switch inverter, the link current equals a phase current only during specific switching states: in the active vectors (one high-side and two low-side devices on, or the reverse) the link current equals one phase current, with the sign determined by which device is on; in the zero vectors (all high or all low) the link current is zero. The reconstruction algorithm therefore samples the link current twice per PWM period (in the two adjacent active vectors) and derives the third phase current from the Kirchhoff relation ia + ib + ic = 0. Constraints: the two sampling windows must each be long enough for the amplifier to settle and the ADC to convert, so the technique fails at high modulation index when one active vector becomes very short (the “measurement dead zone” near full modulation), and it requires the PWM to be organised so that the two windows are always available — usually with a symmetric pattern and a deliberately inserted time-shift at the extremes. Single-shunt reconstruction is attractive in cost-sensitive drives but adds algorithm complexity and a distortion region at the operating extremes; if the application needs full torque at high speed, an inline shunt per phase is usually the better engineering choice.

7. Code Snippet — Offset Calibration and Current Scaling

/* Three-shunt FOC: calibrate offsets with the bridge disabled, then
   scale raw ADC counts to amperes. Sample synchronously with the PWM
   centre via the timer's ADC trigger. */

#define ADC_FULL_SCALE   4095.0f
#define VREF             3.300f
#define CSA_GAIN         50.0f      /* V/V */
#define R_SHUNT          0.002f     /* 2 mOhm, 20 A -> 40 mV, x50 = 2.0 V */
#define V_BIAS           1.650f     /* mid-rail reference of the CSA */
#define I_MAX            20.0f

typedef struct { float offset; float scale; } phase_cal_t;

static phase_cal_t cal[3];

/* Call once, with all gate outputs disabled and the motor at rest. */
void current_calibrate(void)
{
    uint32_t acc[3] = {0, 0, 0};
    const int N = 256;

    for (int n = 0; n < N; ++n) {
        acc[0] += adc_read(PHASE_A_CH);
        acc[1] += adc_read(PHASE_B_CH);
        acc[2] += adc_read(PHASE_C_CH);
    }
    for (int p = 0; p < 3; ++p)
        cal[p].offset = (float)acc[p] / (float)N;   /* counts at I = 0 */

    /* counts -> amperes: (v - v_bias) / (gain * r_shunt) / counts_per_volt */
    const float counts_per_volt = ADC_FULL_SCALE / VREF;
    for (int p = 0; p < 3; ++p)
        cal[p].scale = 1.0f / (CSA_GAIN * R_SHUNT * counts_per_volt);
}

static inline float current_read(int phase, uint16_t raw)
{
    /* The calibration offset is the mid-rail code; subtract it first so
       that offset drift and reference drift are both removed. */
    return (float)raw - cal[phase].offset; /* counts relative to zero current */
}

/* Called from the ADC-conversion-complete interrupt. The timer triggers
   the conversion at the PWM counter peak, so this value approximates the
   average phase current of the period. */
void foc_current_isr(uint16_t ra, uint16_t rb, uint16_t rc)
{
    float ia = current_read(0, ra) * cal[0].scale;
    float ib = current_read(1, rb) * cal[1].scale;
    float ic = current_read(2, rc) * cal[2].scale;

    /* Sanity: the three currents must sum to ~0. A persistent residual
       indicates a mis-scaled channel or a sampling-timing error. */
    float residual = ia + ib + ic;
    if (fabsf(residual) > 0.02f * I_MAX)
        current_fault_count++;

    foc_update(ia, ib, ic);
}

The calibration step is worth emphasising: with a 2 mΩ shunt, a 100 µV amplifier offset is 50 mA of apparent current, and the ADC’s own offset and reference tolerance add to it. Calibrating at power-up (and periodically, if the temperature drifts significantly) removes most of that error and is essentially free. Note also that the sign conventions must be consistent with the PWM’s definition of positive current direction — a sign error in one phase produces a control loop that appears to fight itself, a symptom that is frequently misdiagnosed as a motor parameter error.

8. Worked Example — 48 V, 20 A FOC Drive

Target: a 48 V BLDC drive, 20 A continuous (40 A peak), 20 kHz centre-aligned PWM, three inline shunts, FOC with a 4 kHz current loop, ambient inside the enclosure 60 °C.

• Shunt: 2 mΩ, 3 W, 50 ppm/°C, four-terminal Kelvin, metal element. At 20 A RMS: V_sense = 40 mV, P = 0.8 W (well within the 3 W rating even at 100 °C derating); at 40 A peak: 80 mV, 3.2 W for the short peak duration — check the pulse rating. The 0.8 W dissipation inside the enclosure is part of the thermal budget and must be added to the bridge and amplifier losses.
• Amplifier: a current-sense amplifier with 50 V/V gain, ±150 µV maximum offset, 400 kHz bandwidth, common-mode range from −0.3 V to +70 V. Full-scale output at 20 A: 40 mV × 50 = 2.0 V plus the 1.65 V bias = 3.65 V — that exceeds a 3.3 V ADC range, so reduce the gain to 40 V/V (1.6 V + 1.65 V = 3.25 V, still tight) or lower the shunt to 1.5 mΩ. This gain/rail interaction is easy to miss and shows up as clipping exactly at the current where the drive needs linearity for protection.
• Error budget at 20 A: shunt tolerance 0.5%, shunt tempco over a 40 °C rise 0.2%, amplifier gain error 0.5%, amplifier offset 150 µV → 0.4% of the 40 mV signal (but 7.5% at 2 A and 75% at 0.2 A), ADC reference and INL 0.3%. Total at full scale ≈ 1.5%; at 10% load ≈ 4% dominated by offset. If the application needs 2% torque accuracy at low load, the offset must be calibrated (as in the code above) or a chopper amplifier used.
• Bandwidth and settling: the current loop runs at 4 kHz (period 250 µs); the amplifier’s 400 kHz bandwidth gives a settling time well under 5 µs, and the RC input filter is set at 200 kHz so it does not dominate. Blanking after each commutation edge: 1.5 µs to let the common-mode transient settle, then sample at the PWM counter peak.
• Protection path: a separate analogue comparator on the amplified signal, with a threshold at 45 A and a propagation delay under 2 µs, drives the gate driver’s disable input directly — the firmware’s protection cannot be relied on alone, since its worst-case latency includes the ADC, the interrupt and the loop’s own execution.
• Verification: (1) compare the sensed current with a calibrated current probe at 1, 5, 20 and 40 A, at several modulation indices; (2) check the zero-current residual over temperature; (3) inject a fast current step and measure the settling; (4) run the drive at the extremes of the modulation range (the low-side sensing dead zone does not apply to inline sensing, but the common-mode stress is highest there); (5) thermal soak with the drive at rated current and verify the shunt’s temperature rise and the amplifier’s offset drift.

9. Common Mistakes

• Ignoring the amplifier’s common-mode range: an inline shunt needs a common-mode range above the bus voltage plus overshoot, or the input stage clips and the reading is silently wrong at the switching edges.
• Sampling away from the PWM centre: the measured current then includes the ripple asymmetrically, producing a torque error that varies with the duty cycle.
• No blanking after the switching edge: ringing on the sense signal at the sampling instant produces random current spikes that trip protection and inject noise into the loop.
• Single-ended sense routing: the measurement then includes the solder-joint and trace resistances, and drifts with temperature at a different rate from the shunt’s own tempco.
• Relying on firmware for overcurrent protection: the trip must be in hardware, with the firmware as a secondary, slower check.
• Forgetting the shunt’s dissipation in the enclosure’s thermal budget: 0.8 W per shunt inside a sealed drive is a real contribution to the internal temperature.
• Calibrating with the bridge enabled: the offsets then include the switching noise and the calibration is worse than useless.

10. FAQ

Q: How many sense resistors do I need? A: Three for the most demanding FOC (independent phase currents, no reconstruction constraints); two if one phase can be reconstructed (the sum of the three currents is zero in a three-wire motor); one DC-link shunt if cost dominates and the operating range stays away from the reconstruction dead zones.

Q: Can I measure current with the MOSFETs’ RDS(on)? A: Yes, in low-cost drives, but the RDS(on) varies strongly with temperature and part-to-part, and the sense signal is available only while the switch is on; the gain error over temperature is typically several percent without compensation.

Q: What sampling rate does the current loop need? A: A common rule is one current sample per PWM period for the loop plus additional samples for protection; the loop bandwidth is then roughly 1/10 of the sampling rate.

Q: Does the shunt’s inductance really matter? A: At 20 kHz with tens of nanoseconds of edge rate, a few nanohenries produce a voltage spike comparable to the signal during the switching transient; it affects protection and the blanking requirement more than the average current measurement.

Q: How do I verify the current sense in production? A: Test the zero-current offset and gain against a calibrated reference at one or two points, and store the calibration coefficients in the device’s memory; a full multipoint calibration is rarely necessary after the design is validated.

11. Conclusion

Motor current sensing is a signal-integrity problem wrapped in a control problem. Choose the sensing topology from the common-mode and sampling-window constraints, size the shunt from the loss and signal budget, pick an amplifier for offset rather than for bandwidth alone, route the sense pair with Kelvin connections and a quiet reference, sample at the PWM centre with adequate blanking, and put overcurrent protection in hardware. Do these and the control loop has the feedback it needs; skip any one and the symptom will appear as a mysterious torque ripple, an unexplained protection trip or a drive that works in the lab and fails at temperature.