1. Introduction — At High Speed the Copper Is the Circuit

At low frequency a PCB trace is a lumped wire: connect point A to point B and the schematic works. Above a few tens of MHz (or when rise times fall below about a nanosecond), the same trace becomes a transmission line whose characteristic impedance, delay, crosstalk and return path decide whether the signal arrives intact. High-speed routing is the discipline of controlling those physics: choosing a stack-up with controlled impedance planes, routing as controlled-impedance traces over continuous reference planes, matching lengths where skew matters, guarding against crosstalk and via transitions, decoupling the planes for power integrity, and keeping the return current path short. This guide covers the routing procedures that turn a schematic into a board that actually passes the high-speed interface — emphasizing the decisions that a router makes and the physics each one obeys.

2. Transmission-Line Fundamentals for Routing

A trace over a solid reference plane has characteristic impedance Z0, which for an edge-coupled microstrip is approximated by:

Z0 ≈ 87/√(εr + 1.41) · ln(5.98·h / (0.8w + t))

and for a stripline by:

Z0 ≈ 60/√εr · ln( 4h / (0.67π·(0.8w + t)) )

where w is trace width, h the dielectric height to the reference plane, t the copper thickness and εr the dielectric constant. The rise time of the driving signal, not the clock frequency alone, decides whether a net is “high speed”. When the one-way trace delay exceeds roughly 1/6 of the signal rise time, terminations and impedance control become mandatory. A fast rule of thumb: signals with rise times under 1 ns for traces longer than a few cm need transmission-line treatment; the site’s decoupling capacitor calculator and controlled stack-up design (see the PCB stackup guide) support the power and impedance decisions that routing depends on.

3. Router Plan — Before the First Trace

3.1 Assign critical nets and planes

• Identify differential pairs, clock nets, reset, and data groups; give each a routing class with impedance and length rules.
• Assign continuous GND reference planes under every high-speed layer; never route a critical trace over a split plane.
• Budget the stack-up (e.g. JLC04161H-7628 or a 4-layer 1.6 mm FR4 with 50 Ω single-ended / 90 Ω differential targets) and ask the fab for the exact widths.

3.2 The routing order

Route in this order: power-critical and thermal-critical paths first? No — route the most timing-sensitive, impedance-controlled signals first on the planes adjacent to the reference, then the less critical buses, then the analog sensitive nets away from aggressors, and finally route the power and low-speed control logic that tolerate more freedom. This ordering protects the signals that can actually break the design from being squeezed by the noise-tolerant 90%.

4. Crosstalk and Spacing

Adjacent parallel traces couple capacitively and inductively; the interference at the victim depends on the spacing-to-height ratio s/h. Increasing s/h from 1 to 3 typically cuts near-end crosstalk by roughly 10 dB or more; a common class rule is 3W spacing (three times the trace width) for moderate-risk nets and 5W for sensitive ones. Additional techniques: route aggressor and victim on different layers (with a solid plane between them), limit parallel run length, and stagger parallel segments so coupling is not resonant. Differential pairs should be routed tightly coupled (edge-to-edge spacing about 2× width) because their crosstalk immunity relies on identical coupling to both legs; breaking a pair’s symmetry converts common-mode noise into differential signal.

5. Length Matching and Skew

Parallel buses equalize propagation delay so all bits arrive within the same window. The delay of a trace is about τ = 85–150 ps/cm depending on the dielectric: FR4 microstrip ~143 ps/inch (56 ps/cm), stripline ~180 ps/inch. Length matching tolerances derive from the interface data window, not from fashion: for DDR3 address/control vs clock tolerance is commonly ±20 mils per byte-lane-ish budgets, while high-pin-count serial interfaces (e.g. JESD204, wide LVDS) set their own skew budgets. When a meander is needed, use accordion or zig-zag shapes with a minimum section length well above the coupling length so that the added parallel runs do not create their own crosstalk hotspots.

6. Vias, Transitions and Reference-Plane Bridges

Every via adds inductance (~0.5–1 nH per via for a through-hole) and a capacitive stub; avoid vias in the middle of a tightly length-matched segment of a straight high-speed trunk, and stagger breaks. When a signal must change layers, provide a stitching via or an adjacent return via so the return current can jump planes without ringing; otherwise the return path detours through bypass caps and the EMI/crosstalk budget collapses. For serialize interfaces, ground vias adjacent to the signal via (a “via fence”) improve the transition. Keep high-speed nets away from the board edge (≥ 3–5 mm) to avoid edge coupling and manufacturing tolerance surprises.

7. Power Integrity and Decoupling as Routing

High-speed routing is not finished when the signals are clean — the supply planes must carry the switching current without the planes ringing. Place the high-frequency decoupling capacitors at the load pins, with short low-inductance connections to the planes; this is precisely where the decoupling capacitor calculator finds its use: computing the resonant frequency and effective series inductance (ESL) from capacitor value and mounting parasitics so the anti-resonance between different value caps is managed rather than discovered at bring-up. Route the return current of every high-speed signal directly above/below its source/sink path; a single unbroken GND plane is the cheapest and most effective filtering device on the board. When board-level EMI is a risk, the input filtering strategy of the EMI filter calculator complements the layout by attenuating the conducted noise at the connector.

8. Worked Example — Routing a 90 Ω Differential USB 2.0 Pair on a 4-Layer Board

Target: USB 2.0 D+/D− at 480 Mb/s, differential impedance 90 Ω, on a 4-layer 1.6 mm FR4 stack-up with L2/L3 as GND/power planes.

• Read the fab table: for a 0.2 mm dielectric (7628) microstrip, the recommended width for 90 Ω differential is typically 0.15 mm with 0.15 mm spacing; confirm from the fab’s impedance table.
• Route both legs on L1 over the solid L2 GND plane; keep the pair together edge-to-edge, symmetrical, with no long point where one leg goes around an obstacle alone.
• Length-match D+ and D− to within ±1 mm; add the meander on the shorter leg.
• Add a series termination (e.g. 22 Ω) placed at the driver, and a 15 kΩ pull-down/pull-up bias network near the connector as required by the spec.
• Ground stitch the connector shield; keep the pair ≥ 2× pair width from adjacent nets.
• Verify with the controlled stack-up rules and the 3W spacing on both sides; from the decoupling calculator place a 0.1 µF + 1 µF at the USB transceiver pins with short vias to L2.

9. Common Mistakes

• Splitting the reference plane: a critical trace crossing a split returns through a detour and radiates; if a split is unavoidable, add a bridge capacitor or a stitching via next to the crossing.
• Routing a differential pair’s two legs on different lengths or layers: imbalance destroys the common-mode rejection the pair was designed to provide.
• Oversized meanders: long parallel sections in the meander create their own crosstalk and extra delay; keep the sections short and matched.
• Over-via-ing the signal: each via adds stub and inductance; minimize transitions on high-speed trunks.
• Ignoring the return path of decoupling caps: a bypass cap far from the pin or connected through a long trace is decorative.
• Treating ground pours as reference: filled, segmented copper with slots does not behave like a plane; use real, continuous, unbroken planes.

10. FAQ

Q: When is a signal “high speed”? A: When its rise time is short compared to the round-trip delay of the trace — roughly when the one-way delay exceeds ~1/6 of the rise time; this can happen at a 10 MHz signal with 2 ns edges.

Q: Is a ground pour acceptable as a reference? A: Only if it is a true, unbroken plane on a full layer; a grid or slotted pour leaves the return current wandering.

Q: Why must differential pairs stay symmetric? A: Each leg couples equally to noise only when the geometry is symmetric; the pair’s rejection of common-mode noise depends entirely on that symmetry.

Q: How much spacing is enough? A: Start from the crosstalk requirement: 3W for moderate, 5W for sensitive, plus layer separation where possible — then verify with field solvers on tight interfaces.

11. Conclusion

High-speed routing is the controlled application of transmission-line, crosstalk and power-integrity physics to copper. Plan the stack-up and routing classes, keep continuous reference planes, match lengths, manage vias and decoupling, and verify every decision against the interface’s real timing budget. When a quick decoupling or EMI filter math check helps, the calculators on this site remove the guesswork from the layout decisions.