Decoupling Capacitor Calculator — InnovChip

Decoupling Capacitor Calculator

Size board-level decoupling for digital ICs from load-step, rise time and target ripple, and cross-check via target impedance at frequency.

Calculator

About This Calculator

Fast current steps from switching digital loads cause supply droop. The ΔV method sizes bulk decoupling as C = I·Δt/ΔV for the biggest step within the slew window. The target-impedance method instead requires Z ≤ ΔV/I up to the noise frequency. This calculator does both and recommends the larger value.

How to Use

  1. Estimate the worst-case load step (A) and how fast it happens (ns) — chip datasheets and reference designs usually state both.
  2. Set the max ripple your rail can tolerate in mV.
  3. Use the recommended value, then distribute it as a mix: bulk (10-100 µF) + MLCC (0.1-1 µF) near the pins.
  4. Check the impedance-based figure separately if the noise bandwidth is high — it often dominates.

Formulas

ΔV methodC(min) = I(step) × t(rise) / ΔV
Target impedanceZ(target) = ΔV / I(step)
Impedance methodC = 1 / (2π f Z(target))

Design Notes

MLCC derate cap dramatically with DC bias — 10 µF in 0402 may measure 3 µF at 3.3 V. Oversize accordingly.

Place smallest capacitors closest to the package pins to minimize loop inductance.