1. GPIO Configuration That Does Not Bite Back

GPIO looks simple — set a pin high or low, read a pin state. But GPIO configuration is where most bring-up bugs live. An STM32 pin can be an input, output, alternate function (AF), or analog mode. Each has sub-options: pull-up, pull-down, open-drain, push-pull, and speed grade.

Output Speed — Not Just Faster Is Better

STM32 GPIO pins have configurable slew rates: Low, Medium, High, and Very High. Faster edges improve signal integrity for SPI above 20 MHz but increase EMI and power consumption. For a 9600-baud UART TX line, Low is more than enough. For SPI at 36 MHz, use High. Match speed to the fastest signal on that pin, not the chip’s maximum. HAL initialization:

GPIO_InitTypeDef gpio = {0};
gpio.Pin = GPIO_PIN_13;
gpio.Mode = GPIO_MODE_OUTPUT_PP;
gpio.Pull = GPIO_PULLUP;
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOB, &gpio);

Common pitfalls: forgetting __HAL_RCC_GPIOB_CLK_ENABLE(), configuring I2C pins in push-pull instead of open-drain, and leaving unused pins floating (increases leakage — set them to analog mode).

2. Timer Peripherals — The Swiss Army Knife

STM32 timers come in three tiers: basic (TIM6/TIM7), general-purpose (TIM2-TIM5, TIM9-TIM14), and advanced-control (TIM1/TIM8/TIM20). Each tier adds real hardware capabilities.

PWM Frequency Formula

PWM frequency: PWM_Freq = TIM_CLK / ((PSC + 1) * (ARR + 1)). For 50 Hz servo PWM on a 72 MHz APB1 timer: PSC=1439 (tick at 50 kHz), ARR=999 (period at 50 Hz, 1000-step resolution). In HAL:

htim2.Init.Prescaler = 1439;
htim2.Init.Period = 999;
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);

Input Capture

Input capture latches the counter on a rising/falling edge. Capture both edges to compute pulse width and period. Handle timer overflow in the update interrupt and add ARR+1 to the calculation when the counter wraps.

3. ADC and DAC — Bridging Analog and Digital

ADC: Getting Real-World Data In

Most STM32s have 12-bit successive-approximation ADCs (0-4095 counts). The critical parameter: sampling time. The sample-and-hold capacitor must charge through the external source impedance. Too short a sampling time with a high-impedance source gives wrong readings. For sources under 1k, 3 cycles is fine; for 10k-50k, use 28-84 cycles; above 50k, buffer with an op-amp.

Scan Mode + DMA

For multiple channels, pair scan mode with DMA in circular mode. The ADC sequences through channels and DMA fills a buffer continuously — no CPU intervention:

uint16_t adc_buffer[4];
HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_buffer, 4);
// adc_buffer updated continuously, CPU reads at leisure

DAC: Generating Analog Outputs

The 12-bit DAC outputs 0 to VREF+ (typically 3.3V). Trigger it with a timer for waveform generation — a 100 kHz update rate with DMA-fed samples gives a basic function generator. Add an external op-amp buffer because the DAC output impedance is high.

4. DMA — Stop Wasting CPU Cycles

DMA transfers data between peripherals and memory without CPU involvement. STM32 has two controllers (DMA1, DMA2), each with streams and channels. A stream is a transfer engine; a channel selects which peripheral triggers it. Always check your part’s DMA request mapping table.

The DMA + UART Pattern

For variable-length UART reception, use UART IDLE detection with DMA on F0/F3/F4/F7/G0/G4/H7/L4:

HAL_UARTEx_ReceiveToIdle_DMA(&huart1, rx_buffer, RX_BUF_SIZE);
// HAL_UARTEx_RxEventCallback() fires when line goes idle

This eliminates the old “poll until timeout” hacks that waste CPU and add latency.

5. Serial Communication — SPI, I2C, and UART

SPI: Speed Over Distance

SPI is full-duplex, master-driven, with SCK, MOSI, MISO, and NSS. The critical parameters: CPOL (clock idle polarity) and CPHA (sampling edge), defining SPI modes 0-3. Most devices use Mode 0 or 3 — confirm from the slave datasheet. For high-speed SPI above 20 MHz, keep traces under 50 mm and use 22-47 ohm series resistors near the driver.

I2C: Two Wires, One Headache

I2C uses SDA and SCL, both open-drain with external pull-ups. Pull-up sizing: 4.7k for standard mode (100 kHz), 2.2k for fast mode (400 kHz), 1.0k for fast-mode plus (1 MHz). Estimate bus capacitance at 10 pF per device + 3 pF per cm of trace. If the bus hangs, clock out 9 extra SCK pulses to release a stuck slave.

UART: The Workhorse

UART is asynchronous — both sides agree on baud, data bits, stop bits, and parity. Use the STM32 Clock Configuration Calculator to verify baud accuracy. For reliable reception, use hardware flow control (RTS/CTS) or an application protocol with start/end delimiters, length byte, and checksum.

6. NVIC and Interrupt Management

The Nested Vectored Interrupt Controller handles up to 240 external interrupt lines with configurable priorities. Priority is split into preemption (can interrupt a lower-priority ISR) and sub-priority (decides order when two same-preemption interrupts are pending).

Use 4 bits of preemption, 0 bits of sub-priority (NVIC_PriorityGroup_4) — 16 levels of pure nesting, simple and predictable. Cortex-M interrupt latency is 12 cycles, but tail-chaining cuts it to 6 cycles between back-to-back interrupts. Keep ISRs short: do the minimum work, set a flag, handle the rest in the main loop.

EXTI for External Signals

For button presses and sensor alerts, configure EXTI lines with trigger edges:

HAL_NVIC_SetPriority(EXTI15_10_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);

Do not debounce inside the ISR. Capture a timestamp and check the stable state after a 20-50 ms window in the main loop.

7. Watchdog Timers — Your Silent Guardian

IWDG: Independent Protection

The Independent Watchdog runs from its own internal 32 kHz LSI oscillator. If the main oscillator fails or code hangs, the IWDG still ticks and forces a reset if not refreshed. A 1-2 second timeout works for most applications:

hiwdg.Init.Prescaler = IWDG_PRESCALER_64;  // 32kHz / 64 = 500 Hz
hiwdg.Init.Reload = 1000;                   // 2-second timeout
HAL_IWDG_Init(&hiwdg);
// In main loop: HAL_IWDG_Refresh(&hiwdg);

WWDG: Catching Timing Violations

The Window Watchdog runs from PCLK1 and must be refreshed within a time window. Refresh too late or too early and it resets. This catches code running at the wrong rate — exactly the bug IWDG would miss. Ideal for control loops with precise timing requirements.

8. Low-Power Modes — Sleep, Stop, and Standby

Battery-powered STM32 applications depend on low-power design. The Cortex-M core offers three modes:

Sleep is for waiting on a peripheral interrupt — call __WFI(). Stop preserves SRAM, wakes on RTC alarm or EXTI — ideal for sensor nodes. Standby loses SRAM, wakes through full reset — for coin-cell devices waking a few times per day.

Low-Power Checklist

1. Disable unused peripheral clocks — each adds 10-100 μA.
2. Set unused GPIOs to analog mode (lowest leakage).
3. Disable debug module in Stop/Standby (DBGMCU->CR = 0).
4. Use LSE (32.768 kHz crystal) for RTC — more accurate and lower power than LSI.
5. Reduce system clock before entering Stop for flash power savings.
6. On L4/L5/U5 families, use the SMPS regulator for ~40% run-mode savings.

9. System Design Walkthrough: A Battery Data Logger

A practical design: a battery-powered data logger reading two sensors (temperature via ADC, pressure via I2C), timestamping via RTC, buffering via DMA, and sending packets over UART. 48-hour battery target.

Between samples, the STM32 enters Stop mode. Every second, RTC wakes the CPU. The ISR triggers an ADC read (DMA handles the result), reads I2C pressure (3-byte transaction), formats a packet, and returns to Stop. Active time per sample: under 500 μs. Average current: ~120 μA. With a 2000 mAh battery, that is over 16,000 hours — far exceeding the 48-hour requirement. Each peripheral does one job, and reliability comes from clean partitioning.

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