STM32 Clock Configuration Guide
HSE, PLL, Prescalers & System Clock Setup
STM32 Clock Configuration Guide
Master STM32 clock configuration from scratch. Learn how to select HSI, HSE, PLL sources, configure system clocks, and optimize for performance vs. power consumption — with practical STM32CubeMX examples.
Configure Your STM32 Clock Instantly
Use our interactive STM32 Clock Config Calculator to generate PLL parameters, system clock trees, and peripheral clock outputs.
Open STM32 Clock Calculator →What Is STM32 Clock Configuration?
The STM32 clock system is the heartbeat of the microcontroller. It distributes clock signals from multiple sources to the CPU core, bus matrix (AHB, APB1, APB2), and all peripherals. Proper clock configuration is essential because it directly determines processing performance, power consumption, peripheral timing accuracy, and system stability.
STM32 microcontrollers offer exceptional flexibility: you can choose between internal RC oscillators, external crystals, or a PLL that multiplies frequencies up to the device maximum. However, this flexibility also creates a common source of confusion — especially when configuring PLL dividers, selecting the right HSE bypass mode, or setting the correct AHB/APB prescalers.
Modern STM32 families (F0, F1, F3, F4, F7, G0, G4, H5, H7, L0–L5, U5, WB, WL) each have unique clock tree topologies with different maximum frequencies and PLL configurations. Despite these differences, the fundamental concepts — clock source selection, PLL multiplication, and bus prescaling — remain consistent across all series. Understanding these core principles allows you to configure any STM32 device with confidence.
This guide covers every aspect of STM32 clock configuration with clear examples and practical advice, from basic HSI-only operation to advanced multi-PLL setups for demanding applications like USB OTG, Ethernet, camera interfaces, and high-speed ADC sampling.
The STM32 clock system is the heartbeat of the microcontroller. It distributes clock signals from multiple sources to the CPU core, bus matrix (AHB, APB1, APB2), and all peripherals. Proper clock configuration is essential because it directly determines processing performance, power consumption, peripheral timing accuracy, and system stability.
STM32 microcontrollers offer exceptional flexibility: you can choose between internal RC oscillators, external crystals, or a PLL that multiplies frequencies up to the device maximum. However, this flexibility also creates a common source of confusion — especially when configuring PLL dividers, selecting the right HSE bypass mode, or setting the correct AHB/APB prescalers.
This guide covers every aspect of STM32 clock configuration with clear examples and practical advice.
Core Formula: STM32 System Clock Calculation
Calculating the STM32 system clock frequency involves understanding the clock tree and the PLL multiplier/divider chain. The general formula for the system clock (SYSCLK) using PLL is shown below.
STM32 PLL Output Formula
PLLCLK = (Source / M) × N / P
Where:
- Source = HSI (8/16 MHz), HSE (4–50 MHz), or MSI
- M = PLL input divider (1–63, must produce 1–8 MHz at PLL input)
- N = PLL multiplier (8–432, VCO output = PLL input × N)
- P = PLL output divider (2, 4, 6, 8 — produces PLLCLK)
- Q = USB/SDIO/RNG divider
- R = Additional divider (on some series)
Constraints: VCO frequency must be between 64–432 MHz (varies by series). PLL input (Source/M) must be 1–8 MHz.
Worked Example: 168 MHz on STM32F4 with HSE 8 MHz
Given: HSE crystal = 8 MHz, Target SYSCLK = 168 MHz (STM32F407 max)
Step 1: Set M = 4, PLL input = 8 / 4 = 2 MHz (within 1–8 MHz range)
Step 2: Set N = 336, VCO frequency = 2 MHz × 336 = 672 MHz (within 64–432 MHz? No — need to adjust)
Revision: Use M = 4, N = 168: VCO = 2 × 168 = 336 MHz (valid). P = 2: PLLCLK = 336 / 2 = 168 MHz.
AHB Prescaler: HPRE = 1 (no division) → HCLK = 168 MHz
APB2 Prescaler: PPRE2 = /2 → APB2 clock = 84 MHz (max for F4 APB2 bus)
APB1 Prescaler: PPRE1 = /4 → APB1 clock = 42 MHz (max for F4 APB1 bus is 42 MHz)
Result: SYSCLK = 168 MHz, HCLK = 168 MHz, APB1 = 42 MHz, APB2 = 84 MHz
Clock Source Parameter Table
| Clock Source | Typical Freq | Accuracy | Best For |
|---|---|---|---|
| HSI (Internal RC) | 8, 16, 48, 64 MHz | ±1% | Boot, low-cost, low-accuracy designs |
| HSE (External Crystal) | 4–50 MHz | ±10–50 ppm | High-accuracy, USB, Ethernet, CAN |
| MSI (Multi-Speed Internal) | 100 kHz – 48 MHz | ±0.25% (trimmed) | Ultra-low-power, L-series, stop modes |
| LSE (Low-Speed External) | 32.768 kHz | ±5 ppm | RTC calendar, low-power wake-up |
| LSI (Low-Speed Internal) | 32–40 kHz | ±5% | IWDG, RTC backup, low-cost RTC |
Understanding the STM32 Clock Tree from Source to Peripheral
The clock tree follows a structured hierarchy: a clock source (HSI/HSE/MSI) is fed into the PLL for multiplication, producing SYSCLK. SYSCLK is divided by the AHB prescaler (HPRE) to generate HCLK (the main bus clock for CPU, memory, and DMA). HCLK feeds the APB1 prescaler (PPRE1) and APB2 prescaler (PPRE2), producing the peripheral bus clocks PCLK1 and PCLK2. Importantly, when APB prescalers divide by more than 1, the timer clocks (TIMxCLK) are doubled relative to the APB bus clock, allowing timers to run at up to the HCLK frequency even on slower peripheral buses.
Clock Tree Configuration Checklist for STM32CubeMX
- Step 1: Select HSE or HSI as the PLL source on the “Clock Configuration” tab
- Step 2: Enter your desired HCLK frequency in the “HCLK (MHz)” field
- Step 3: CubeMX automatically computes M, N, P, and prescaler values — review for constraint violations
- Step 4: Verify USB (48 MHz) and RTC (LSE/LSI) clock sources are configured
- Step 5: Set Flash wait states (WS) according to the resulting HCLK frequency
- Step 6: Disable unused peripheral clocks in the “RCC” peripheral configuration
Common STM32 Clock Configuration Mistakes
Frequently Asked Questions
1. What is the default STM32 clock source after reset?
After reset, STM32 devices boot using the HSI (High-Speed Internal) oscillator, typically running at 8 MHz (or 16 MHz on newer series). The system clock (SYSCLK) defaults to HSI divided by 8 (1 MHz on F4 series). This safe boot mode ensures reliable startup regardless of external crystal status.
2. How do I know if my HSE crystal value is valid?
Check the PLL input constraints: Source/M must be 1–8 MHz. Common HSE values: 8 MHz (direct PLL input with M=2,4,8), 12 MHz (M=3 or 6), 16 MHz (M=4 or 8), 25 MHz (M=5, common for H7 Ethernet/USB). The crystal load capacitance (CL) must also match the PCB layout — typically 12–20 pF.
3. How do I configure the STM32 PLL for maximum frequency?
For maximum SYSCLK: choose HSE as the PLL source for best accuracy, minimize the M divider to keep PLL input above 1 MHz (ideally 2 MHz), maximize the N multiplier within the VCO range, and set P = 2 for the smallest output division. Example for STM32F446 (max 180 MHz): HSE = 8 MHz, M = 4 (PLL input = 2 MHz), N = 180 (VCO = 360 MHz, within 64–432 MHz), P = 2 → PLLCLK = 180 MHz. For STM32H743 (max 480 MHz): HSE = 25 MHz, M = 5 (PLL1 input = 5 MHz), N = 96 (VCO = 480 MHz), P = 1 → PLL1P = 480 MHz. Use STM32CubeMX or our interactive calculator to automatically find valid parameter combinations for your specific target frequency and device.
4. Why does my STM32 not boot after changing clock settings?
Common causes: (1) PLL parameters out of range (VCO or divider), (2) Flash wait states too low for new frequency, (3) HSE crystal not oscillating (check bypass vs. crystal mode), (4) APB prescaler exceeding bus limits. Solution: reflash with a known-good configuration via ST-Link, verify clock source, and incrementally increase frequency.
5. How do I generate a 48 MHz clock for USB?
Use the PLL Q output: after configuring the main PLL to your target SYSCLK, set PLLQ to divide the VCO frequency down to exactly 48 MHz. The VCO frequency after N multiplication must be divisible by Q to produce 48,000,000 exactly. For STM32F4 with 168 MHz SYSCLK (8 MHz HSE, M=4, N=336, P=2): VCO = 336 MHz, Q = 7 gives 48.000 MHz (336/7 = 48). For 180 MHz on STM32F446 (M=4, N=180, VCO=360 MHz): Q = 7.5 is invalid — use a different clock configuration like 8 MHz HSE with M=4, N=192, P=4 (48 MHz SYSCLK) and Q=4 for 48 MHz. On STM32H7, the USB clock can also come from PLL3Q for greater flexibility. Always verify with an oscilloscope on the USB DP line during SOF packets.
6. What is the difference between HSI and HSE?
HSI is an internal RC oscillator — fast startup (a few μs), no external components, but lower accuracy (±1%) and temperature stability. HSE uses an external crystal or oscillator — higher accuracy (±10–50 ppm), temperature stable, but requires two PCB pins and external components, with longer startup time (~1–2 ms).
7. How do I reduce STM32 power consumption via clock configuration?
Reduce SYSCLK frequency to the minimum required for your application. Use lower AHB/APB prescalers to reduce dynamic power. Switch to MSI (L-series) for ultra-low-power run. Use clock gating to disable unused peripheral clocks. Enter sleep/stop/standby modes and use LSI or LSE for low-power wake-up timing.
8. What clock do I need for Ethernet MAC (STM32F4/F7/H7)?
STM32 Ethernet MAC needs a 25 MHz clock (external PHY) or an RMII reference clock. For RMII: 50 MHz from PHY or generated via PLL. On STM32F407 with 25 MHz HSE: M=5, N=200, P=2 gives 100 MHz SYSCLK; Q=?? for 50 MHz RMII. Many designs use a dedicated 25 MHz HSE for both PHY and MCU.
Related Calculators
This article belongs to the Embedded Systems category on InnovChip Tools.