CAN Bus Bit Timing Calculator

This tool calculates the critical bit timing parameters required to configure a CAN controller: BRP (Baud Rate Prescaler), TSEG1 (Time Segment 1), TSEG2 (Time Segment 2), and SJW (Synchronization Jump Width). It ensures the configured timing meets the target bit rate and sample point while respecting hardware constraints of CAN 2.0B controllers.

The sample point determines when the CAN controller samples the bus level to interpret a bit value—typically set between 75%–90% of the bit time for robust noise immunity. A well-placed sample point avoids sampling during signal transitions or recessive-to-dominant edges, reducing errors caused by ringing or propagation delay.

“CAN Clock” is the input clock frequency feeding the CAN peripheral (e.g., APB1 clock on STM32). “Target Bit Rate” is the desired nominal bit rate (e.g., 125 kbps or 1 Mbps). “SJW” (Synchronization Jump Width) limits how far the controller can adjust phase segments during resynchronization—critical for tolerating oscillator drift and network jitter.

Per ISO 11898-1, TSEG1 typically ranges from 2 to 16 time quanta (TQ), and TSEG2 from 2 to 8 TQ—though some controllers support wider ranges. The sum TSEG1 + TSEG2 + 1 equals the total bit length in TQ. This tool enforces standard-compliant values and flags invalid combinations.

This occurs when the requested bit rate and sample point cannot be achieved with integer-valued prescaler and segment settings given the CAN clock frequency and hardware limits. Try adjusting the sample point (±5%), relaxing SJW, or verifying the clock source accuracy—some microcontrollers require specific clock dividers to reach common CAN rates.

No—this calculator is designed exclusively for classical CAN 2.0B (up to 1 Mbps). CAN FD uses separate timing configurations for the arbitration and data phases, plus additional parameters like transceiver delay compensation. Use a dedicated CAN FD bit timing calculator for those applications.

The prescaler divides the CAN clock to generate time quanta (TQ); smaller BRP values yield coarser timing resolution but lower overhead, while larger BRP improves sample point precision at the cost of reduced maximum bit rate. A very high BRP may increase susceptibility to oscillator tolerance errors—aim for BRP ≥ 2 and minimize unnecessary scaling.

For bit rates ≤ 125 kbps, ±1.58% tolerance is generally acceptable; for 500 kbps, aim for ≤ ±0.5%; and for 1 Mbps, ≤ ±0.3%. This tool doesn’t calculate tolerance margins—but if your design targets automotive or industrial environments, always verify that the final timing solution meets the worst-case oscillator drift + propagation delay budget.

Not necessarily—the tool uses the user-provided SJW as a constraint, not an optimization target. While SJW = 1 minimizes resynchronization latency, higher values (e.g., SJW = 2 or 4) improve tolerance to phase errors in noisy or long-bus systems. Choose SJW based on your network’s oscillator stability and physical layout—not just what “fits”.

Map the calculated BRP, TSEG1, TSEG2, and SJW directly to your MCU’s CAN registers (e.g., BTR on STM32, CBT on NXP S32K). Then verify operation using a CAN analyzer or oscilloscope: check bit width consistency, sample point position (via edge-triggered capture), and error frame count under load. Simulate bus stress with termination mismatches to confirm robustness.