Watchdog Timeout Calculator

This tool calculates the actual timeout periods (in milliseconds and seconds) for both Independent Watchdog (IWDG) and Window Watchdog (WWDG) timers on STM32 microcontrollers. It uses LSI clock frequency, prescaler, reload value, and (for WWDG) window value to determine the minimum and maximum time windows before a reset is triggered.

IWDG provides simple timeout-based reset protection with no early-warning window, while WWDG requires servicing within a precise time window—too early triggers an immediate reset, too late causes timeout reset. The calculator shows both behaviors so you can select or validate the appropriate watchdog mode for your safety-critical application.

The Low-Speed Internal (LSI) RC oscillator (~32 kHz) is independent of the main system clock and remains active during STOP modes—making it ideal for reliable watchdog operation. Its inherent ±10% tolerance means calculated timeouts should include margin; this tool assumes nominal 32 kHz unless adjusted.

The prescaler divides the LSI clock frequency before feeding it to the counter; larger prescaler values increase timeout. The 12-bit reload value sets the counter’s initial count—higher values extend timeout linearly. Together, they define the base timeout: T = (LSI / PSC) × (RELOAD + 1) for IWDG.

For IWDG: reload values commonly range from 0x0FF (255) to 0xFFF (4095), yielding ~8 ms to ~1.3 s at 32 kHz/64 prescaler. For WWDG: window values must be less than reload (e.g., 0x40–0x7F) and ≥0x40 to avoid spurious resets; reload is typically 0x7F–0xFF. Always verify against your MCU’s datasheet limits.

Common causes include LSI clock inaccuracy (±10%), incorrect prescaler selection (some MCUs only support specific values like 4/8/16/32/64/128/256), or misconfigured WWDG window timing. Ensure your code writes the same reload/window values and enables the watchdog correctly—this tool assumes ideal conditions and doesn’t model startup delays or register write sequences.

Yes—it supports early design validation of watchdog timing margins. However, functional safety compliance requires additional analysis: worst-case clock drift, interrupt latency, software servicing overhead, and fault injection testing. Use this tool to establish baseline timeouts, then add ≥2× safety margin and document assumptions per your ASIL level.

The window value defines the earliest point (relative to counter wrap) at which the WWDG can be refreshed. If refreshed before this window opens, a reset occurs immediately. The calculator computes both the *minimum* refresh interval (based on window) and *maximum* (based on reload), defining the valid service window.

Yes—your IWDG timeout must exceed worst-case firmware initialization time (clock setup, peripheral config, memory tests). If boot takes 500 ms, set reload/prescaler for ≥750 ms timeout. This tool helps size that margin; always measure actual boot time on target hardware under temperature/voltage extremes.

Leaving the window value empty disables WWDG-specific calculations—the tool displays only IWDG timeout results. To calculate WWDG parameters, enter a valid window value less than the reload value (and ≥0x40 for most STM32 families). Invalid window entries trigger a warning and skip WWDG output.