STM32 ADC Configuration Calculator

This tool calculates key timing and performance parameters for STM32 microcontroller ADCs: total conversion time (including sampling + conversion), maximum achievable sampling rate (SPS), effective resolution considering input impedance and sampling time, and recommended external trigger timing margins. It also flags potential configuration conflicts (e.g., insufficient sampling time for given input impedance).

STM32 ADC accuracy depends heavily on source impedance charging the internal sampling capacitor within the selected sampling time. Higher Z_IN requires longer sampling cycles to avoid gain error and nonlinearity. The calculator uses Z_IN to validate whether your chosen sampling time meets the 1/2 LSB settling requirement per AN4073 and RM0433 guidelines.

Valid values depend on the STM32 series and ADC resolution. Common settings include 1.5 (fastest, lowest accuracy), 7.5 (default for medium-speed applications), 13.5, 28.5, 41.5, 81.5, and 239.5 (slowest, highest accuracy). Values must match the hardware’s supported cycle options—non-integer steps like 7.5 reflect the internal clock cycle count (e.g., 7.5 ADCCLK cycles).

ADC clock (ADCCLK) directly determines conversion speed: a higher ADCCLK reduces total conversion time but may degrade SNR if it exceeds the datasheet’s maximum rating (typically ≤14 MHz for 12-bit accuracy on most STM32 families). The calculator warns when ADCCLK violates device-specific limits or causes undersampling of the analog signal.

Set mode = 1 for single-conversion mode (one-shot, triggered manually or by event), ideal for low-power or infrequent measurements. Set mode = 0 for continuous mode (repeated conversions), used in real-time monitoring or DMA streaming. The calculator adjusts effective sample rate and power estimates accordingly—continuous mode increases average current draw and thermal noise considerations.

For multi-channel sequences (e.g., regular or injected groups), total sequence time equals the sum of sampling + conversion time per channel. The calculator computes aggregate throughput (samples/sec across all channels) and highlights bottlenecks—especially critical when using DMA with circular buffers or time-triggered acquisitions requiring precise inter-channel spacing.

Yes—the calculator derives minimum trigger interval requirements based on your configured conversion time and mode. It also suggests safe trigger setup margins (e.g., ≥2× conversion time) to prevent missed triggers or overrun errors, and flags cases where hardware trigger sources may not support your desired sampling rate due to timer resolution limits.

Lower resolution modes reduce the required settling precision (e.g., 10-bit needs ~1/1024 settling vs. 12-bit’s 1/4096), allowing shorter sampling times—and thus higher throughput—for the same input impedance. The calculator dynamically adjusts minimum viable sampling cycles and highlights trade-offs between speed, accuracy, and noise immunity.

It prevents undersampling-induced gain error (due to insufficient sampling time), clock-related inaccuracies (ADCCLK > max rated frequency), resolution mismatches (e.g., 12-bit config with 6-bit sampling time), and timing violations in triggered or continuous sequences. Real-time warnings appear for configurations likely to cause data corruption or degraded ENOB.

It models behavior common to mainstream STM32 lines (F0/F1/F3/F4/G0/G4/H7/L0/L4) using generic ADC architecture rules. However, advanced features (e.g., dual-mode interleaving, oversampling, or V_REFINT calibration) require family-specific validation. Always cross-check results against your target MCU’s Reference Manual (RMxxxx) and datasheet timing diagrams.