STM32 Timer Calculator

This tool calculates the optimal prescaler (PSC) and auto-reload register (ARR) values for STM32 general-purpose timers to achieve precise timing goals—such as PWM frequency, periodic interrupts, or input capture intervals. It accounts for timer clock source, bit-width (16/32-bit), and user-defined targets like frequency or period. Results are validated against hardware constraints (e.g., maximum ARR = 2ⁿ−1).

Enter your timer’s APB clock frequency (e.g., 72 MHz), desired PWM frequency (e.g., 20 kHz), and duty cycle (e.g., 75%). The tool computes PSC and ARR to set the base period, then derives the compare register (CCR) value for the specified duty cycle. Ensure your selected timer channel is configured in PWM mode in HAL/LL code.

This is the actual clock frequency fed to the timer peripheral—typically the APB1 or APB2 bus clock, which may be prescaled from the system clock (e.g., TIM2 on APB1@36 MHz when SYSCLK=72 MHz). Check your STM32 reference manual (RCC section) and CubeMX clock configuration to confirm the exact timer clock source and frequency.

A 16-bit timer supports ARR values up to 65,535; a 32-bit timer supports up to 4,294,967,295. Higher bit-width allows finer resolution at low frequencies or longer periods without increasing the prescaler excessively. Use 32-bit for ultra-low frequencies (<1 Hz) or high-precision timing; 16-bit suffices for most PWM and interrupt applications.

This indicates the requested timing target exceeds the timer’s capability with the given clock and bit-width. For example, requesting a 1 Hz output on a 16-bit timer with a 72 MHz clock requires ARR > 65,535—so either increase the prescaler manually (if overflow occurs), switch to 32-bit mode, or reduce the timer clock (e.g., via APB prescaler) before re-calculating.

Yes. Set “Target Frequency” to your expected input signal’s max frequency (to avoid overflow), or use “Target Period” for known pulse widths. The calculator provides PSC/ARR to achieve desired timer resolution (e.g., 1 µs ticks). Then configure the timer in input capture mode and scale captured CNT values using the computed tick duration.

Timer Clock: 1–200 MHz (matches common STM32 families); Target Frequency: 0.001 Hz to ~100 MHz (limited by PSC/ARR constraints); Duty Cycle: 0–100%; Bits: 16 or 32 only; Target Period: 1 ns to seconds (practical limit depends on clock & bit-width). Values outside these ranges often trigger invalid or saturated results.

Use the computed PSC and ARR values to initialize TIMx->PSC and TIMx->ARR registers. For PWM, set TIMx->CCR1 (or CCRx) to (ARR + 1) × duty / 100. In HAL, pass these to __HAL_TIM_SET_PRESCALER(), __HAL_TIM_SET_AUTORELOAD(), and __HAL_TIM_SET_COMPARE(), or configure them via CubeMX’s graphical timer setup.

No—it assumes the “Timer Clock (MHz)” you enter is the *final* frequency delivered to the timer after all APB prescalers (e.g., PCLK1_DIV2). You must determine that value yourself from your RCC setup (e.g., using STM32CubeMX clock tree or HAL_RCC_GetPCLK1Freq()). Incorrect timer clock input will lead to inaccurate timing.

Yes. Configure for your desired delay (e.g., 500 ms) using the “Target Period” field. The resulting PSC/ARR defines the timeout interval. In code, enable the timer’s one-pulse mode (TIM_OPMODE_SINGLE) and wait for the update interrupt (UIF) or use polling on TIM_FLAG_UPDATE.