Stripline Impedance Calculator

This tool calculates the characteristic impedance (Z₀) of a symmetric stripline — a signal trace embedded between two parallel ground planes in a PCB’s inner layer. It uses the standard closed-form approximation for homogeneous dielectric environments and accounts for trace width, plane spacing, dielectric constant, and copper thickness. The result helps ensure signal integrity in high-speed digital and RF designs.

Use stripline for controlled-impedance routing on inner PCB layers where superior EMI shielding, consistent impedance, and lower crosstalk are required — especially in high-frequency (>500 MHz), mixed-signal, or noise-sensitive applications. Microstrip is preferred for outer-layer traces due to simpler fabrication, but stripline offers better isolation and dispersion performance at the cost of higher layer count and tighter fabrication tolerances.

Trace Width (W) is the conductor’s lateral dimension on the PCB layer. Plane Spacing (H) is the distance from the trace centerline to each adjacent ground plane (i.e., total dielectric thickness divided by 2). Dielectric εᵣ is the relative permittivity of the PCB substrate (e.g., FR-4 ≈ 4.2–4.6). Copper Thickness (T) affects current-carrying capacity and effective trace geometry; it’s used to adjust the effective width in impedance models.

Common values include: W = 0.1–2.0 mm (often 0.2–0.5 mm for 50 Ω), H = 0.1–0.8 mm (e.g., 0.2–0.4 mm for standard 4-layer boards), and εᵣ = 3.8–4.8 for FR-4, or 2.2–3.5 for specialized low-loss laminates like Rogers RO4003C. Always verify εᵣ at your target frequency, as it decreases slightly with rising frequency.

Thicker copper reduces the effective trace resistance and slightly increases the effective width due to sidewall taper (especially in etched traces), lowering impedance. While many simplified formulas ignore T, this calculator applies a correction factor per IPC-2141A and industry-standard approximations to improve accuracy—critical for tight-tolerance designs (e.g., ±5% impedance control).

No — characteristic impedance (Z₀) is a *distributed* property dependent only on geometry and material, not length. However, trace length directly impacts propagation delay, loss (dB/mm), phase shift, and termination requirements. This tool includes length input to support downstream calculations (e.g., delay estimation or loss modeling), but it does not influence the Z₀ result.

Verify units (W and H in mm, T in μm), ensure symmetric stripline assumptions apply (equal spacing to both planes), and confirm your stackup matches the model (no adjacent signal layers, uniform dielectric). Also check if your εᵣ value reflects frequency-dependent behavior — using a DC εᵣ for GHz signals may overestimate Z₀. Small changes in W or H dominate sensitivity; a ±0.05 mm error in H can shift Z₀ by ~5 Ω.

This tool implements the widely accepted Hammerstad & Jensen approximation, validated against measurement and full-wave solvers (e.g., HFSS) within ±3–5% for typical PCB geometries. It’s suitable for pre-layout design and iterative tuning. For critical applications (e.g., >10 Gbps serial links), always validate final stackup and trace dimensions with 2.5D/3D EM simulation or TDR measurement.

No — this tool assumes perfect symmetry: identical dielectric thickness above and below the trace, and homogeneous εᵣ. Asymmetric striplines (e.g., trace offset toward one plane) require different formulas or field solvers. For such cases, consider using a dedicated asymmetric stripline calculator or modeling in a 2.5D solver that supports non-uniform layer heights.

Characteristic impedance (Z₀) refers to a single-ended trace referenced to ground planes. Differential impedance (Z_diff) applies to tightly coupled trace pairs (e.g., USB, PCIe) and depends on both Z₀ and coupling coefficient. While this tool computes single-ended Z₀, you can estimate Z_diff ≈ 2×Z₀×(1−k), where k is coupling (typically 0.1–0.3); for precise results, use a dedicated differential stripline calculator.