PCB Thermal Via Calculator

This tool calculates the minimum number of thermal vias required beneath a heat-generating component (e.g., MOSFET, IC, or power regulator) to achieve a target junction-to-ambient thermal resistance. It uses conduction-based thermal modeling through plated vias in FR-4 or similar PCB substrates, assuming steady-state conditions and dominant via conduction (not convection or radiation).

Use thermal vias when you need localized, low-resistance heat transfer from surface-mount components into internal or bottom-layer copper planes—especially in compact designs without space for heatsinks or fans. They’re ideal for power ICs, DC-DC converters, LED drivers, and RF amplifiers where board-level thermal management is critical.

Copper plating thickness (typically 15–35 µm in standard PCB fabrication) determines the effective cross-sectional area of the via barrel wall, directly impacting its thermal conductance. Thinner plating increases thermal resistance; values below 15 µm may require derating or verification with your PCB fabricator.

The model assumes idealized conditions: uniform plating, no solder mask coverage over vias, perfect thermal contact between component pad and vias, and negligible interfacial resistance. Real-world performance may vary by ±20–30% due to manufacturing tolerances, solder voiding, and plane connectivity—always validate with thermal simulation or IR imaging.

Common thermal via diameters range from 0.2 mm (8 mil) to 0.4 mm (16 mil); smaller vias allow higher density but reduce per-via conductance. Standard board thicknesses are 0.8 mm, 1.0 mm, 1.6 mm (most common), or 2.0 mm. Thicker boards increase thermal resistance linearly—so more vias are needed unless using staggered or blind vias.

The calculator determines the number of vias needed to limit *temperature rise* (ΔT = T_j − T_a) — a relative value independent of absolute ambient. Since thermal resistance R_θJA = ΔT / P, only the allowable rise (e.g., 40°C) and power matter for via sizing; ambient sets the absolute operating temperature but not the required conduction path.

No—the model assumes standard round, plated-through holes with annular rings. Non-circular shapes (e.g., slots) or conductive-filled vias alter thermal paths significantly and require finite-element analysis. For epoxy- or copper-filled vias, treat them as solid cylinders with adjusted effective conductivity (~2–5× improvement over standard plated vias).

Calculate vias per pad independently using localized power dissipation and pad area. For stacked (microvia + through-hole) structures, sum the thermal conductances in parallel—but verify manufacturability and reliability (e.g., CTE mismatch, voiding). This tool assumes single-layer via stacks; multi-stack analysis requires advanced thermal modeling tools.

Double-check input units (e.g., copper plating in µm, not mm), ensure power dissipation reflects peak steady-state—not transient—values, and verify that your target ΔT is realistic. High counts often indicate insufficient copper area, excessive power, or inadequate board material; consider adding inner-layer thermal planes or switching to metal-core PCBs.

This calculator complements—but does not replace—IPC standards. IPC-2152 provides current-carrying capacity and trace heating data; IPC-2221 gives general design rules. Thermal via design falls outside these documents’ scope, so this tool applies fundamental conduction physics aligned with industry best practices used in power electronics layout guidelines.